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    CS2000P-DZZ 参数 Datasheet PDF下载

    CS2000P-DZZ图片预览
    型号： CS2000P-DZZ
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10]
    分类和应用： 光电二极管
    文件页数/大小： 30 页 / 944 K
    品牌： CIRRUS [ CIRRUS LOGIC ]
     浏览型号CS2000P-DZZ的Datasheet PDF文件第2页浏览型号CS2000P-DZZ的Datasheet PDF文件第3页浏览型号CS2000P-DZZ的Datasheet PDF文件第4页浏览型号CS2000P-DZZ的Datasheet PDF文件第5页浏览型号CS2000P-DZZ的Datasheet PDF文件第6页浏览型号CS2000P-DZZ的Datasheet PDF文件第7页浏览型号CS2000P-DZZ的Datasheet PDF文件第8页浏览型号CS2000P-DZZ的Datasheet PDF文件第9页  
    CS2000-OTP
    Fractional-N Clock Synthesizer & Clock Multiplier
    Features
    Delta-Sigma Fractional-N Frequency Synthesis
    General Description
    The CS2000-OTP is an extremely versatile system
    clocking device that utilizes a programmable phase lock
    loop. The CS2000-OTP is based on a hybrid analog-
    digital PLL architecture comprised of a unique combina-
    tion of a Delta-Sigma Fractional-N Frequency
    Synthesizer and a Digital PLL. This architecture allows
    for both frequency synthesis/clock generation from a
    stable reference clock as well as generation of a low-jit-
    ter clock relative to an external noisy synchronization
    clock with frequencies as low as 50 Hz. The CS2000-
    OTP has many configuration options which are set once
    prior to runtime. At runtime there are three hardware
    configuration pins available for mode and feature
    selection.
    The CS2000-OTP is available in a 10-pin MSOP pack-
    age in Commercial (-10°C to +70°C) and Automotive-D
    (-40°C to +85°C) and Automotive-E (-40°C to +105°C)
    grades. Customer development kits are also available
    for custom device prototyping, small production pro-
    gramming, and device evaluation. Please see
    “Ordering
    Information” on page 29
    for complete details.
    –
    Generates a Low Jitter 6 - 75 MHz Clock
    from an 8 - 75 MHz Reference Clock
    Generates a Low Jitter 6 - 75 MHz Clock
    from a Jittery 50 Hz to 30 MHz Clock
    Source
    Maximum Error Less Than 1 PPM in High-
    Resolution Mode
    Configurable Hardware Control Pins
    Configurable Auxiliary Output
    External Oscillator or Clock Source
    Supports Inexpensive Local Crystal
    No External Analog Loop-filter
    Components
    Clock Multiplier / Jitter Reduction
    –
    Highly Accurate PLL Multiplication Factor
    –
    One-Time Programmability
    –
    –
    –
    –
    –
    Flexible Sourcing of Reference Clock
    Minimal Board Space Required
    3.3 V
    Timing Reference
    Frequency Reference
    PLL Output
    Lock Indicator
    Hardware Control
    Hardware Configuration
    Auxiliary
    Output
    8 MHz to 75 MHz
    Low-Jitter Timing Reference
    Fractional-N
    Frequency Synthesizer
    6 to 75 MHz
    PLL Output
    Output to Input
    Clock Ratio
    N
    50 Hz to 30 MHz
    Frequency Reference
    Digital PLL & Fractional
    N Logic
    Output to Input
    Clock Ratio
    http://www.cirrus.com
    Copyright
    Cirrus Logic, Inc. 2009–2015
    (All Rights Reserved)
    Cirrus Logic Confidential
    OCT '15
    DS758F3

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