CS2000-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T = -10°C to +70°C (Commercial Grade);
A
T = -40°C to +85°C (Automotive-D Grade); T = -40°C to +105°C (Automotive-E Grade); C = 15 pF.
A
A
L
Parameters
Symbol
Conditions
Min
Typ
Max Units
Crystal Frequency
Fundamental Mode XTAL
fXTAL
8
16
32
-
-
-
14
28
50
MHz
MHz
MHz
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
Reference Clock Input Frequency
fREF_CLK
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
8
16
32
-
-
-
14
28
56
MHz
MHz
MHz
Reference Clock Input Duty Cycle
Internal System Clock Frequency
Clock Input Frequency
DREF_CLK
fSYS_CLK
fCLK_IN
45
8
-
55
14
30
%
MHz
MHz
50 Hz
-
Clock Input Pulse Width (Note 4)
pwCLK_IN
fCLK_IN < fSYS_CLK/96
fCLK_IN > fSYS_CLK/96
2
10
-
-
-
-
UI
ns
Clock Skipping Timeout
tCS
fCLK_SKIP
fCLK_OUT
tOD
(Notes 5, 6)
(Note 6)
20
-
-
-
80
75
55
3.0
3.0
-
ms
kHz
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
50 Hz
(Note 7)
6
45
-
-
MHz
%
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note 8)
50
1.7
1.7
70
50
175
tOR
ns
Clock Output Fall Time
tOF
-
ns
Period Jitter
tJIT
-
ps rms
ps rms
ps rms
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN (Note 11)
(Notes 8, 9)
-
-
(Notes 8, 10)
-
-
tLC
fCLK_IN < 200 kHz
fCLK_IN > 200 kHz
-
-
100
1
200
3
UI
ms
PLL Lock Time - REF_CLK
tLR
ferr
fREF_CLK = 8 to 75 MHz
-
1
3
ms
Output Frequency Synthesis Resolution (Note 12)
High Resolution
High Multiplication
0
0
-
-
±0.5
±112
ppm
ppm
Notes: 4. 1 UI (unit interval) corresponds to t
or 1/f
.
SYS_CLK
SYS_CLK
5.
t
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
CS
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
.
CS
6. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 15 for more information.
7.
8.
f
f
is ratio-limited when f
is below 72 Hz.
CLK_IN
CLK_OUT
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
9. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
10. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
11. 1 UI (unit interval) corresponds to t
or 1/f
.
CLK_IN
CLK_IN
12. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
8
DS761F3
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