CS2000CP-EZZ 参数 Datasheet PDF下载

型号：	CS2000CP-EZZ
PDF下载：	下载PDF文件查看货源
内容描述：	[Phase Locked Loop,]
分类和应用：	光电二极管
文件页数/大小：	37 页 / 1274 K
品牌：	CIRRUS [ CIRRUS LOGIC ]

CS2000-CP

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 5

2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7

RECOMMENDED OPERATING CONDITIONS .................................................................................... 7

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7

DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8

PLL PERFORMANCE PLOTS ............................................................................................................... 9

CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................. 10

CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11

4. ARCHITECTURE OVERVIEW ............................................................................................................. 12

4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12

4.2 Hybrid Analog-Digital Phase Locked Loop .................................................................................... 12

4.2.1 Fractional-N Source Selection for the Frequency Synthesizer .............................................. 13

5. APPLICATIONS ................................................................................................................................... 14

5.1 Timing Reference Clock Input ........................................................................................................ 14

5.1.1 Internal Timing Reference Clock Divider ............................................................................... 14

5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 15

5.1.3 External Reference Clock (REF_CLK) .................................................................................. 15

5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 15

5.2.1 CLK_IN Skipping Mode ......................................................................................................... 15

5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 17

5.3 Output to Input Frequency Ratio Configuration ............................................................................. 19

5.3.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 19

5.3.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 19

5.3.3 Ratio Modifier (R-Mod) .......................................................................................................... 20

5.3.4 Effective Ratio (REFF) .......................................................................................................... 20

5.3.5 Fractional-N Source Selection ............................................................................................... 21

5.3.6 Ratio Configuration Summary ............................................................................................... 22

5.4 PLL Clock Output ........................................................................................................................... 23

5.5 Auxiliary Output .............................................................................................................................. 23

5.6 Clock Output Stability Considerations ............................................................................................ 24

5.6.1 Output Switching ................................................................................................................... 24

5.6.2 PLL Unlock Conditions .......................................................................................................... 24

5.7 Required Power Up Sequencing .................................................................................................... 24

6. SPI / I²C CONTROL PORT ................................................................................................................... 24

6.1 SPI Control ..................................................................................................................................... 25

6.2 I²C Control ...................................................................................................................................... 25

6.3 Memory Address Pointer ............................................................................................................... 27

6.3.1 Map Auto Increment .............................................................................................................. 27

7. REGISTER QUICK REFERENCE ........................................................................................................ 27

8. REGISTER DESCRIPTIONS ................................................................................................................ 28

8.1 Device I.D. and Revision (Address 01h) ........................................................................................ 28

8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 28

8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 28

8.2 Device Control (Address 02h) ........................................................................................................ 28

8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 28

8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 28

8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 29

8.3 Device Configuration 1 (Address 03h) ........................................................................................... 29

8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 29

8.3.2 Ratio Selection (RSel[1:0]) .................................................................................................... 29

DS761F3

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