CobraNet Hardware User’s Manual
Synchronization
5.0 Synchronization
Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design
(CM-2). This circuitry allows the synchronization modes documented below to be
achieved. Modes are distinguished by different settings of the multiplexors and software
elements.
MCLK_OUT
VCXO
24.576 MHz
CS1810xx/CS4961xx
DAC
AClkConfig
FS1
Audio
Clock
Generator
SLCK
MCLK_IN
Sample
Phase
Counter
MCLK_SEL
Phase
Detector
Loop
Filter
RefClkEnable
RefClkPolarity
Edge
Detect
REFCLK_IN
BeatReceived
Legend:
External
Internal
Hardware
Component
(CM2)
Hardware
Component
(CS1810xx, CS4961xx)
Software
Component
Figure 3. Audio Clock Sub-system
5.1 Synchronization Modes
Clock synchronization mode for conductor and performer roles is independently
selectable via management interface variables syncConductorClock and
syncPerformerClock. The role (conductor or performer) is determined by the network
environment including the conductor priority setting of the device and the other devices on
the network. It is possible to ensure you will never assume the conductor role by selecting
a conductor priority of zero. However, it is not reasonable to assume that by setting a high
conductor priority, you will always assume the conductor role. For more information, refer
to CobraNet Programmer’s Reference Manual.
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
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