CobraNet Hardware User’s Manual
List of Figures
List of Figures
Figure 1. CobraNet Data Services .........................................................................................................5
Figure 2. CobraNet Interface Hardware Block Diagram.........................................................................8
Figure 3. Audio Clock Sub-system.......................................................................................................17
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) -
CS18100x/CS49610x & CS18101x/CS49611x............................................................19
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) -
CS18102x/CS49612x...................................................................................................19
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1.....................................20
Figure 7. Serial Port Data Timing Overview.........................................................................................20
Figure 8. Audio Data Timing Detail - Normal Mode, 64FS -
CS18100x/CS49610x, CS18101x/CS49611x ..............................................................21
Figure 9. Audio Data Timing Detail - Normal Mode, 128FS -
CS18102x/CS49612x...................................................................................................21
2
Figure 10. Audio Data Timing Detail - I S Mode, 64FS -
CS18100x/CS49610x, CS18101x/CS49611x ..............................................................21
2
Figure 11. Audio Data Timing Detail - I S Mode, 128FS -
CS18102x & CS49612x................................................................................................21
Figure 12. Audio Data Timing Detail - Standard Mode, 64FS -
CS18100x/CS49610x, CS18101x/CS49611x ..............................................................22
Figure 13. Audio Data Timing Detail - Standard Mode, 128FS -
CS18102x/CS49612x...................................................................................................22
Figure 14. Host Port Read Cycle Timing - Motorola Mode ..................................................................25
Figure 15. Host Port Write Cycle Timing - Motorola Mode...................................................................25
Figure 16. Parallal Control Port - Intel Mode Read Cycle ....................................................................27
Figure 17. Parallel Control Port - Intel Mode Write Cycle ....................................................................27
Figure 18. CM-2 Module Assembly Drawing, Top ...............................................................................38
Figure 19. CM-2 Module Assembly Drawing, Bottom ..........................................................................39
Figure 20. General PCB Dimensions...................................................................................................40
Figure 21. Example Configuration, Side View......................................................................................41
Figure 22. Faceplate Dimensions ........................................................................................................42
Figure 23. Connector Detail .................................................................................................................43
Figure 24. CM-2 RevF Schematic Page 1 of 7 ....................................................................................44
Figure 25. CM-2 RevF Schematic Page 2 of 7 ....................................................................................45
Figure 26. CM-2 RevF Schematic Page 3 of 7 ....................................................................................46
Figure 27. CM-2 RevF Schematic Page 4 of 7 ....................................................................................47
Figure 28. CM-2 RevF Schematic Page 5 of 7 ....................................................................................48
Figure 29. CM-2 RevF Schematic Page 6 of 7 ....................................................................................49
Figure 30. CM-2 RevF Schematic Page 7 of 7 ....................................................................................50
Figure 31. 144-Pin LQFP Package Drawing........................................................................................51
Figure 32. Device Part Numbering Explanation...................................................................................53
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©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
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