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    CRD42L51 参数 Datasheet PDF下载

    CRD42L51图片预览
    型号： CRD42L51
    PDF下载： 下载PDF文件 查看货源
    内容描述： 低功耗立体声编解码器与耳机放大器 [Low Power, Stereo CODEC with Headphone Amp]
    分类和应用： 解码器编解码器放大器
    文件页数/大小： 88 页 / 1582 K
    品牌： CIRRUS [ CIRRUS LOGIC ]
     浏览型号CRD42L51的Datasheet PDF文件第1页浏览型号CRD42L51的Datasheet PDF文件第2页浏览型号CRD42L51的Datasheet PDF文件第3页浏览型号CRD42L51的Datasheet PDF文件第5页浏览型号CRD42L51的Datasheet PDF文件第6页浏览型号CRD42L51的Datasheet PDF文件第7页浏览型号CRD42L51的Datasheet PDF文件第8页浏览型号CRD42L51的Datasheet PDF文件第9页  
    CS42L51
    4.5.3 High-Impedance Digital Output ............................................................................................. 40
    4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 40
    4.6 Digital Interface Formats ................................................................................................................ 40
    4.7 Initialization ..................................................................................................................................... 41
    4.8 Recommended Power-Up Sequence ............................................................................................. 41
    4.9 Recommended Power-Down Sequence ........................................................................................ 42
    4.10 Software Mode ............................................................................................................................. 43
    4.10.1 SPI Control .......................................................................................................................... 43
    4.10.2 I²C Control ........................................................................................................................... 43
    4.10.3 Memory Address Pointer (MAP) .......................................................................................... 45
    4.10.3.1 Map Increment (INCR) ............................................................................................. 45
    5. REGISTER QUICK REFERENCE ........................................................................................................ 46
    6. REGISTER DESCRIPTION .................................................................................................................. 49
    6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 49
    6.2 Power Control 1 (Address 02h) ...................................................................................................... 49
    6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 50
    6.4 Interface Control (Address 04h) ..................................................................................................... 52
    6.5 MIC Control (Address 05h) ............................................................................................................. 53
    6.6 ADC Control (Address 06h) ............................................................................................................ 54
    6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 56
    6.8 DAC Output Control (Address 08h) ................................................................................................ 57
    6.9 DAC Control (Address 09h) ............................................................................................................ 58
    6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ............... 59
    6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 60
    6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 61
    6.13 PCMX Mixer Volume Control:
    PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 62
    6.14 Beep Frequency & Timing Configuration (Address 12h) .............................................................. 62
    6.15 Beep Off Time & Volume (Address 13h) ...................................................................................... 63
    6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 64
    6.17 Tone Control (Address 15h) ......................................................................................................... 65
    6.18 AOUTx Volume Control:
    AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 66
    6.19 PCM Channel Mixer (Address 18h) .............................................................................................. 67
    6.20 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 67
    6.21 Limiter Release Rate Register (Address 1Ah) .............................................................................. 69
    6.22 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 70
    6.23 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 70
    6.24 ALC Release Rate (Address 1Dh) ................................................................................................ 71
    6.25 ALC Threshold (Address 1Eh) ...................................................................................................... 71
    6.26 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 72
    6.27 Status (Address 20h) (Read Only) ............................................................................................... 73
    6.28 Charge Pump Frequency (Address 21h) ...................................................................................... 74
    7. ANALOG PERFORMANCE PLOTS .................................................................................................... 75
    7.1 Headphone THD+N versus Output Power Plots ............................................................................ 75
    7.2 Headphone Amplifier Efficiency ...................................................................................................... 77
    7.3 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 78
    8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 79
    8.1 Auto Detect Enabled ....................................................................................................................... 79
    8.2 Auto Detect Disabled ...................................................................................................................... 80
    9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 81
    9.1 Power Supply, Grounding ............................................................................................................... 81
    9.2 QFN Thermal Pad .......................................................................................................................... 81
    10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 82
    4
    DS679F1

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