CRD4205-1
.
Jumper
JP1
Codec Reset
JP2
3.3 V supply
JP3
Primary Down
JP8
From CNR Bus
Secondary Down
JP4
SDATA_IN0
SDIN Target
JP9
Places pull-up
Primary Down
on Primary Down
when inserted.
Pins 1-2
Reset from CNR
Bus
3.3 V from CNR
Bus
From CNR Bus
Pins 2-3
Force Low
Not Used
Force Low
Force Low
SDATA_IN1
NA
(2 pin jumper)
2.8
Component Selection
Great attention was given to the particular compo-
nents used on the CRD4205-1 board with cost, per-
formance, and package selection as the most
important factors. Listed are some of the guidelines
used in the selection of components:
•
•
No components smaller than 0805 package.
Only single package components passive com-
ponents. No resistor packs. This reduces the
risk of crosstalk between audio signals.
All ICs are surface mount.
Dual footprint for XTAL. Standard H49S and
small circular CA-301 pin in hole package.
•
•
Table 2. CNR Connector Jumper Settings
Note:The CRD4205-1 default positions for all jumpers is
between pins 1-2
JP9 inserts a 1 kΩ pull-up on Primary Down. This
is used to disable on-board audio for motherboards
that have a 10 kΩ pull-down resistor on Primary
Down as required by the CNR 1.1 specification.
In addition, JP3 and JP8 can be used to determine
the clocking mode of the CS4205. The CS4205
supports three clocking modes: oscillator (Osc),
crystal (Xtal), and AC-Link bit clock (BIT_CLK).
This is shown in table 3.
JP8
1-2
1-2
2-3
2-3
1-2
1-2
2-3
2-3
JP3
1-2
2-3
1-2
2-3
1-2
2-3
1-2
2-3
ID
0
0
0
0
0
1
2
3
Osc
Osc
Osc
Osc
Osc
Xtal
Bclk
Bclk
Bclk
PLL
no
yes
yes
yes
no
no
no
no
Frequency
Mode
24.576 MHz
Primary
14.318 MHz
Primary
27.000 MHz
Primary
48.000 MHz
Primary
24.576 MHz
Primary
12.288 MHz Secondary
12.288 MHz Secondary
12.288 MHz Secondary
2.9
EMC Components
Optional capacitors and inductors are included to
help the board meet EMI compliance tests, such as
FCC Part 15. Choose these component values ac-
cording to individual requirements.
3. GROUNDING AND LAYOUT
One of the most critical aspects of PC audio design
is good PC board layout. The PC is a hostile envi-
ronment for audio and good layout is essential for
achieving high audio quality.
The CRD4205-1 is partitioned into a digital and an-
alog sections to help isolate noisy digital circuitry
from quiet analog audio circuitry. The most impor-
tant rule for successful PC audio layout is to keep
all digital signal traces and components over the
digital ground plane, and all analog signal traces
and components over an analog ground plane.
These planes are separated by a minimum of 60 to
100 mils (0.060 to 0.100 inches). Do not allow dig-
ital and analog signals to cross planes, otherwise
digital noise may be induced into the analog signals
and severely reduce audio performance.
The CS4205 is placed at the transition point of the
analog and digital ground planes. The CS4205 pins
are partitioned into analog and digital areas. This is
Table 3. JP8 and JP3 Positions for Each Clock Mode
The CS4205 requires both digital +3.3 V and ana-
log +5 V supply. The digital power is supplied
from the CNR connector. A Motorola MC78M05C
regulates the +12 V supply from the CNR bus
down to a clean +5 V analog supply. This +5 V lin-
ear regulator is used to maintain good audio quali-
ty.
5
CIRRUS [ CIRRUS LOGIC ]
