CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
9.2 CM-2 Schematics
connector
connector.sch
core
core.sch
HRESET#
HRESET#
HRESET#
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HEN#
HRW
HDS#
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
HACK#
HACK#
WATCHDOG
MUTE#
WATCHDOG
MUTE#
WATCHDOG
MUTE#
UART_TX_OE
UART_TXD
UART_RXD
UART_TX_OE
UART_TXD
UART_RXD
UART_TX_OE
UART_TXD
UART_RXD
MCLK_OUT
MCLK_IN
REFCLK_IN
MCLK_OUT
MCLK_IN
REFCLK_IN
MCLK_OUT
MCLK_IN
REFCLK_IN
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
GPIO[0..1] is not used elsewhere.
These pulldowns are used for test points and
to keep these signals at valid levels.
GPIO[0..1]
GPIO[0..1]
RSVD[1..5]
AUX_POWER[0..3]
GPIO0
GPIO1
R1
R2
RSVD[1..5]
AUX_POWER[0..3]
RSVD[1..5]
AUX_POWER[3..0]
GND
10K Ohm
This linear regulator is used to assure that the +1.8v rail quickly passes
the 0.5v threshold at powerup, thus minimizing power sequencing issues
and making sure that the DSP does not draw excessive power as the
power rails ramp up. This linear regulator is set with Vout=1.22v, so it
is effectively shut off once the switching regulator comes up. Further
testing and characterization of the DSP is require to determine if this
linear regulator is in fact required.
U9
1
2
4
3
5
IN
OUT
BYP
ADJ
C45
0.01 uF
GND
LTC1761
U1
LTC3406-1.8
L1
4
1
3
5
VCC_+3.3
VIN
SW
VCC_+1.8
2.2 uH
RUN
Vout/FB
C1
10 uF, X5R, 6.3 Volts
C2
C3
10 uF, X5R, 6.3 Volts
This is a simple switching regulator. It produces
1.8V at >500 mA at about 90% efficency. A simple low drop
out linear regulator would be a cheaper alternative at the
expense of power. A linear regulator would dissapate
about 0.75 watts max, This switching regulator dissapates
about 0.10 watts max.
Figure 24. CM-2 RevF Schematic Page 1 of 7
44
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
CIRRUS [ CIRRUS LOGIC ]
