CL-PS7500FE
System-on-a-Chip for Internet Appliance
11. I/O SUBSYSTEMS
11.1 Introduction
CL-PS7500FE has a 16-bit-wide general I/O port, BD[15:0].This allows slow I/O access to continue inde-
pendently of DMA activity on the CL-PS7500FE data bus. There are three types of I/O access supported
over the I/O bus:
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16-MHz, PC-style I/O
8-MHz request/grant-based I/O
simple 8-MHz-based fixed timing I/O
CL-PS7500FE also has a separate 8-bit-wide, general-purpose, open-drain I/O port, each bit of which can
be configured as an interrupt source.There are four analog comparators, each with a 16-bit, 2-MHz timer
that can be a four channel analog joystick interface. Two identical PS/2 serial mouse/keyboard ports are
included. There are two general-purpose, 2-MHz, 16-bit counter timers that can be programmed to pro-
duce interrupts at timed intervals.
CL-PS7500FE includes an interrupt handler, with enable and mask bits for each interrupt source that can
process potential interrupts from a number of internal and external sources.
The 16-MHz, PC-style I/O provides all the signals required to interface with a standard PC Combo chip,
enabling an industry standard part to be used to complete the I/O interfaces to devices such as a floppy
disc.
The facility is available to expand the width of the I/O bus externally by adding latches and buffers to the
upper 16 bits of the main external data bus and control signals for these devices are provided from
CL-PS7500FE.
Support is provided for XIP (execute-in-place) from a 16-bit-wide PCMCIA card attached to the I/O bus,
using an external PCMCIA controller.
Because the I/O clocks can be completely asynchronous to the memory system clock (that controls the
main bus arbitration state machine), there are additional synchronization penalties at the start and end of
the I/O cycle. The exact additional delay depends on the actual phase of the clocks at the point in ques-
tion. The timing diagrams do not attempt to show detail, however, worst-case synchronization delays are
indicated.
11.2 I/O Address Space Usage
The main I/O address space is defined as being from address 0x03000000 to 0x03FFFFFF, as shown in
Table 11-1.
In addition, there is an extended I/O address space for 16-MHz, PC-style I/O from address 0x08000000
up to 0x0FFFFFFF, divided into eight 16-Mbyte areas. The chip select generated throughout this area is
nEASCS.
June 1997
109
ADVANCE DATA BOOK v2.0
I/O SUBSYSTEMS
CIRRUS [ CIRRUS LOGIC ]
