CL-PS7500FE
System-on-a-Chip for Internet Appliance
20. BUS INTERFACE................................................................................................................ 187
20.1
20.2
20.3
20.4
Bus Arbitration................................................................................................................................187
Bus Cycle Types .............................................................................................................................187
Video DMA Bandwidth....................................................................................................................188
Video DMA Latency........................................................................................................................188
21. CLOCKS, POWER SAVING, AND RESET........................................................................ 191
21.1
Clock Control..................................................................................................................................191
21.1.1
21.1.2
21.1.3
21.1.4
21.1.5
Video and Sound Subsystem Clocks..............................................................................191
I/O Clock Outputs ...........................................................................................................191
Synchronous/Asynchronous Mode for the ARM Processor............................................191
Clock Prescalars.............................................................................................................192
Clocking Schemes..........................................................................................................192
21.2
21.3
Power Management........................................................................................................................192
21.2.1
21.2.2
SUSPEND Mode ............................................................................................................193
STOP Mode....................................................................................................................194
Reset ..............................................................................................................................................195
22. ELECTRICAL SPECIFICATIONS ...................................................................................... 196
22.1
22.2
Absolute Maximum Ratings............................................................................................................196
DC Specifications ...........................................................................................................................197
22.2.1
DC Specifications — Digital Values ................................................................................197
22.3
22.4
22.5
22.6
22.7
22.8
Derating..........................................................................................................................................198
AC Parameters — List of Timing Figures .......................................................................................199
System Reset Timing .....................................................................................................................200
Memory Subsystems......................................................................................................................201
I/O Subsystems ..............................................................................................................................209
System Timing (Clocks)..................................................................................................................222
23. PACKAGE ........................................................................................................................... 225
23.1
240-Pin PQFP Package Example...................................................................................................225
24. ORDERING INFORMATION EXAMPLE............................................................................ 226
10
June 1997
TABLE OF CONTENTS
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
