CL-PS7110
Low-Power System-on-a-Chip
BIT INDEX
Numerics
G
64-Hz tick interrupt (TINT) 51
Grayscale enable (GSEN) 53
Grayscale mode (GSMD) 53
A
H
AC prescale 53
HP SIR protocol encoding enable (SIREN) 44
B
I
Battery low interrupt (BLINT) 50
Bit rate divisor 55
Bit to drive buzzer (BZTOG) 44
BOOT8BIT 47
Internal UART enable (UARTEN) 44
Internal UART modem status changed interrupt
(UMSINT) 51
BREAK 56
Buzzer Drive (BZMOD) 44
Internal UART receive FIFO half-full interrupt (URXINT)
51
Internal UART transmit FIFO half-empty interrupt
(UTXINT) 51
C
Inverted NDCDET enable (DCDET) 46
IrDA Tx mode (IRTXM) 45
Clear to send (CTS) 46
Codec interface enable Rx (CDENRX) 44
Codec interface enable Tx (CDENTX) 44
Codec Rx FIFO empty (CRXFE) 47
Codec sound interrupt (CSINT) 50
Codec Tx FIFO full (CTXFF) 47
Cold start flag (CLDFLG) 46
K
Keyboard Scan 43
L
LCD enable bit (LCDEN) 44
Line length 52
D
Data carrier detect (DCD) 46
Data set ready (DSR) 46
Debug enable (DBGEN) 44
Display ID nibble (DID) 46
DRAM refresh enable (RFSHEN) 49
DRAM refresh rate (RFDIV) 50
Drive 0 from battery 54
M
Media changed direct read (MCDR) 46
Media changed interrupt (MCINT) 50
Microwire/SPI peripheral clock speed select
(ADCKSEL) 45
N
Drive 0 from mains 54
Drive 1 pump ratio 54
New battery flag (NBFLG) 46
E
P
Even parity (EVENPRT) 56
Parity enable (PRTEN) 56
Pixel prescale 53
Power fail flag (PFFLG) 46
Expansion clock enable (CLKEN) 49
External expansion clock enable (EXCKEN) 44
External fast interrupt (EXTFIQ) 50
External interrupt input 1 (EINT1) 50
External interrupt input 2 (EINT2) 51
External interrupt input 3 (EINT3) 51
Extra stop (XSTOP) 56
R
Reset flag (RSTFLG) 46
RTC compare match interrupt (RTCMI) 51
RTC divisor output (RTCDIV) 46
F
S
FIFO buffering of Rx and Tx data enable (FIFOEN) 56
Sequential access enable (SQAEN) 49
May 1997
77
DATA BOOK v1.5
BIT INDEX
CIRRUS [ CIRRUS LOGIC ]
