CL-PD6710/’22
ISA–to–PC-Card Host Adapters
For Command Multiplier Value bits, order of reset
states for Timing sets 0 and 1 switched to show
reset state for Timing set 0 first.
Recovery Timing
register reset value changed to
03h to allow additional I/O cycle recovery time of
systems using ’DX/4 processors.
11
12
13
ATA information is now in an application note.
General-purpose strobe chapter added.
Voltage sense chapter added.
11.3
References to -WE and -OE in the last paragraph
have been corrected.
11.4.1The
table on DMA signal usage and Figure 11-2
have been slightly modified.
13
The 144- and 208-pin package drawings have
been updated.
Version 2
Following are major changes between January
1993 and October 1993 versions of this data sheet:
General
A new chip was added: the CL-PD6722.
The CL-PD672X packaging name was changed
to PQFP; the physical package is the same.
The chips are also compatible with PCMCIA 2.1.
Section
2.2
SPKR_OUT*/CSEL pin description in Table 2-1
was changed from TO-PU type to IO-PU type.
Addition of the CL-PD6722 chip changed descrip-
tion in Tables 2-1 and 2-2 of the following pins:
IRQ9, IRQ10, -VPP_VALID, -REG, -OE, -WE,
WP/-IOIS16, -INPACK, and BVD2/-SPKR.
The typical power consumption values in Table
3-1 were updated (reduced) to more closely
reflect expected values.
Sections 3.1.10 and 3.1.11 are new sections
describing the CL-PD6722.
Many indications of Constant bits in registers
were changed from “0” to “Scratch Bit”.
In the Card Status Change register, the Battery
Dead/STSCHG Enable bit name was renamed
Battery Dead Or Status Change Enable.
The Misc Control 2 register bit 6 is not reserved
on the CL-PD6722. Its functionality is described.
Sections 8.6 and 8.7 were added to describe
CL-PD6722–specific registers.
The Setup, Command, and Recovery field names
were altered. The default state for the Command
Multiplier Value field was corrected. The timing
formulas for all three timing register sets were
reformatted. The timing with ‘11’ values selected
on the Prescalar Select field calculate differently.
This new chapter descr ibes DMA on the
CL-PD6722.
Extensive changes were made throughout this
chapter. Please review carefully.
15.1
Allowable voltage on any pin increased to
±0.5
V
greater than voltage of +5V pin.
15.3
Table 15-7: values for t2, t2a, t10, t13, and t18 of
ISA bus timing table changed.
Table 15-9: Pulse mode interrupt timing added.
Table 15-10: General-purpose strobe timing
added.
Table 15-12: values of t5 and t6 of memory
read/write timing table changed.
Table 15-13: -WAIT timing values added to word
I/O read/write timing.
Table 15-17 and 15-18: DMA read and write cycle
timing tables expanded.
16
208-pin VQFP package added.
Version 2.5
Following are major changes between October
1993 and July 1994 versions of this data sheet:
General
An extension register and two bits have been
added to the CL-PD6722 register set.
Section
1.2
5.2
Description for bits labeled Reserved, Compatibil-
ity, 0 or 1, and Scratchpad have been clarified.
In the table for “Bits 1-0: Battery Voltage Detect”,
the column headings for bit 1 and bit 0 were
reversed, and have been corrected.
Bits 6, 3, and 2 (index 2h), bits 6 and 2 (index 7h),
and bit 6 (index 11h, 19h, 21h, 29h, 31h) have
been relabeled Compatibility bits.
Bit 0 (index 36h, 38h) has been relabeled
0.
Bit 1 (index 1Fh) has been changed to be a part
of the CL-PD67XX Revision Level field. Bit 0 has
been relabeled Reserved.
Two bits, Auto-Power Clear and V
CC
Power Lock,
and a register,
Maximum DMA Acknowledge
Delay,
have been added to descriptions of the
CL-PD6722 registers. The
DMA Control
register
was renamed
Extension Control 1.
The Disable
Socket Pull-Ups bit was renamed Pull-Up Control.
3.1
5–9
5
8
5–7
9
6.6
8.4
11
12
8.7
6
TABLE OF CONTENTS
PRELIMINARY DATA SHEET v3.1
May 1997
CIRRUS [ CIRRUS LOGIC ]
