CL-PD6710/’22
ISA–to–PC-Card Host Adapters
2.3 Pin Descriptions
Table 2-1. ISA Bus Interface Pins
Pin Number
CL-PD6710 CL-PD6722
Pin Name
Description
Qty. I/O Pwr. Drive
LA[23:17]
ISA Bus Address Input: Connect to ISA sig- 96, 94, 92, 89, 157, 155, 153,
nals LA[23:17] or, for systems limited to 87, 85, 84
1-Mbyte address space, tie ALE high, ground
LA[23:20] and connect LA[19:17] to ISA sig-
nals SA[19:17].
151, 149, 147,
146
7
I
I
4
4
–
–
SA[16:0]
SD[15:0]
ISA Bus Address Input: Connect to ISA sig- 123:120, 118, 184:181, 179,
nals SA[16:0]. 117, 115, 114, 178, 176, 175,
112, 110, 173, 171,
17
108:106, 104, 169:167, 165,
103, 101, 100 164, 162, 161
ISA Bus Data Input/Output: These pins are 71, 73–75, 77, 134–137,
used to transfer data during a memory or I/O 79–81, 140, 139,
cycle. Connect to ISA signals SD[15:0].
139, 137, 136, 141–143,
134, 132, 130, 200, 199, 197,
12
mA
16
I/O
4
4
For 8-bit system buses, leave SD[15:8] uncon-
nected.
129
196, 194, 193,
190, 189
SBHE*
Byte High Enable: This input is used in con- 98
junction with SA[0] to specify the width and
alignment of a data transfer. Connect to ISA
signal SBHE*.
159
1
I
–
For 8-bit system buses, pull up connect to
ISA_VCC supply.
IOR*
I/O Read: This input indicates that a host
I/O read cycle is occurring. Connect to ISA sig-
nal IOR*.
124
185
186
145
144
180
1
1
1
1
I
I
I
I
4
4
4
4
–
–
–
–
IOW*
I/O Write: This input indicates that a host I/O 125
write cycle is occurring. Connect to ISA signal
IOW*.
MEMR*
MEMW*
REFRESH*
Memory Read: This input indicates that a host 83
memory read cycle is occurring. Connect to
ISA signal MEMR*.
Memory Write: This input indicates that a host 82
memory write cycle is occurring. Connect to
ISA signal MEMW*.
Refresh: This input indicates a memory 119
refresh cycle is occurring and will cause the
CL-PD67XX to ignore memory accesses on
the bus. Connect to ISA signal REFRESH*.
1
1
I
I
4
4
–
–
ALE
Address Latch Enable: A high on this input 105
indicates a valid memory address on the
LA[23:17] bus lines. Connect to ISA signal
BALE.
166
12
May 1997
PIN INFORMATION
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
