CL-GD6420
Notebook VGA Controller
2.
Detailed Pin Description (cont.)
Name
Pin No. Type
Description
RESET
64
65
I
I
SYSTEM RESET: This input is normally connected to the
system reset bus signal and is used as a hardware reset sig-
nal for the CL-GD6420.
AEN
ADDRESS ENABLE: This is a host CPU bus signal that dis-
tinguishes between DMA and non-DMA bus cycles. The sig-
nal is high for a DMA cycle, and will cause the CL-GD6420
to ignore IORD* and IOWR*.
MEMCS16*
12
TO
MEMCS16*: This output is an acknowledge for 16-bit-wide
accesses and is generated by the CL-GD6420 only if the 16-
bit Peripheral Mode is enabled, and a valid memory address
range has been decoded.
IOCHRDY
CRTINT
13
15
TO
TO
O
IOCHRDY: This signal is driven low to lengthen memory cy-
cles.
CRTINT: Indicates the start of a vertical retrace, normally
connected to one of the interrupt inputs on the PC bus.
AA[8:0]
AA[3:0]
137:133
131:128
VIDEO MEMORY ‘A’ ADDRESS BUS: This bus contains
the row/column address information required by the DRAMs
in Video Memory Planes 0 and 1. This bus carries different
addresses than the AB Bus in text modes.
AB[8:4]
AB[3:0]
154:150
148:145
O
VIDEO MEMORY ‘B’ ADDRESS BUS: This bus contains
the row/column address information required by the DRAMs
in Video Memory Planes 2 and 3. This bus carries different
addresses than the AA Bus in text modes.
OE[0]*
138
139
10
O
O
O
VIDEO MEMORY OUTPUT ENABLE BANK 0: For two and
four DRAM configurations.
WE[0]*
VIDEO MEMORY WRITE ENABLE BANK 0: For two and
four DRAM configurations.
PO1/OE[1]*
PROGRAMMABLE OUTPUT #1/VIDEO MEMORY OUT-
PUT ENABLE/WRITE ENABLE BANK 1: For eight-DRAM
configurations.
PO2/WE[1]*
11
O
PROGRAMMABLE OUTPUT #1/VIDEO MEMORY OUT-
PUT ENABLE/WRITE ENABLE BANK 1: For eight DRAM
configurations.
6
July 1993
DATA BOOK
CIRRUS [ CIRRUS LOGIC ]
