CL-GD542X
VGA Graphics Controllers
1.2 Pin Diagram (MicroChannel Bus)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VDD6
MD12
MD11
MD10
MD9
MD8
WE1*
VSS10
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
VSS11
WE0*
CAS*
VSS6
P0
IREF
RED
GREEN
BLUE
EECS
EEDI
AVDD2
OVRW
AVSS2
HSYNC
VSYNC
TWR*
AVDD1
VFILTER
AVSS1
D7
D6
VSS5
D5
D4
VDD3
D3
CL-GD5420/’22/’24/’25/’26/’28/’29
160-Pin PQFP
VDD7
OE*
RAS*
MA9
MicroChannel Bus
VSS12
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
D2
D1
D0
VSS4
-IRQ
UNUSED
-CMD
-S1
-REFRESH
CD_CHRDY
-CD_SETUP
A16
A15
A14
A13
CHRESET
50
49
151
152
48
47
46
45
44
43
42
41
153
154
155
156
157
158
159
160
AVDD4
MFILTER
AVSS4
MCLK
XTAL
OSC
VSS13
NOTES:
1) WE1*, WE0*, MD[15:0], and OVRW are reserved on CL-GD5420.
2) ‘-’ indicates active-low on the MicroChannel bus.
May 1995
3-11
PRELIMINARY DATA BOOK v7.0
PIN INFORMATION
CIRRUS [ CIRRUS LOGIC ]
