Pinout Information
PRELIMINARY DRAFT
Pinout Information
Pinout Diagram
DIAG4
DIAG3
1
156 NC
2
155 NC
DIAG2
3
154 NC
DIAG1
4
153 NC
RF_ENV
CH QUAL MON
AGND
5
152 NC
6
151 AVDD
150 XTALO
149 MCLK2/XTALI
148 AGND
147 BGND
146 MCLK1
145 CLK_OUT
144 uC_CLK
143 CGND
142 DMA33CLK
141 RST*
7
AVDD
8
BGND
9
SDCLK
CKE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DQMU
DQML
BGND
WE*
BVDD
CS0*
140
INT1
CS1*
139 INT2
138 BGND
137 CS*
136 WR*/R/W*
135 RD*/DS
134 A7/ALE
133 A6
CAS*
RAS*
BD15
BD14
BD13
BD12
BVDD
132 A5
CL-CR3710
CVDD
131 A4
BD11
130 BVDD
129 A3
208-Pin LQFP
CGND
BD10
128 CGND
127 A2
BD9/PLL_CLK_BP_SL
BD8/UCSL3
BD7/MOT-I*
BD6/M-NM*
BD5/DEC_CLK_BP_SL
BD4/DTSL
BD3/XTSL
BGND
126 A1
125 A0
124 CVDD
123 AD7
122 BGND
121 AD6
120 AD5
119 AD4
118 AD3
BD2/UCSL2
BVDD
BD1/UCSL1
BD0/UCSL0
BA11
117
AD2
116 AD1
115 AD0
114 EF2
113 BVDD
112 EF1
BA10
BA9
BA8
BA7
BGND
111
BA6
110 EXTC
BA5
109
108
LRCK
BICK
BGND
BA4
107 SDATA
BVDD
106 TEST
BA3
105 TEST_ENBL*
CONFIDEN TIAL
DS587PP1 - rev 0.1 April 11, 2002
Copyright 2002 Cirrus Logic Inc.
13
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CIRRUS [ CIRRUS LOGIC ]
