CS2300-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T = -10°C to +70°C (Commercial Grade);
A
C = 15 pF.
L
Parameters
Symbol
fCLK_IN
Conditions
Min
Typ
Max Units
Clock Input Frequency
Clock Input Pulse Width
50 Hz
-
30
MHz
pwCLK_IN
fCLK_IN < 175 kHz
fCLK_IN > 175 kHz
140
10
-
-
-
-
ns
ns
Clock Skipping Timeout
tCS
fCLK_SKIP
fCLK_OUT
tOD
(Notes 4, 5)
(Note 5)
20
-
-
-
80
75
55
3.0
3.0
-
ms
kHz
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
50 Hz
6
45
-
-
MHz
%
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note 6)
50
1.7
1.7
35
50
150
tOR
ns
Clock Output Fall Time
tOF
-
ns
Period Jitter
tJIT
-
ps rms
ps rms
ps rms
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN (Note 9)
(Notes 6, 7)
-
-
(Notes 6, 8)
-
-
tLC
fCLK_IN < 200 kHz
fCLK_IN > 200 kHz
-
-
100
1
200
3
UI
ms
Notes: 4.
t
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
CS
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
.
CS
5. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 13 for more information.
6. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9. 1 UI (unit interval) corresponds to t
or 1/f
.
CLK_IN
CLK_IN
DS843F1
7
CIRRUS [ CIRRUS LOGIC ]
