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CDK2000-CLK 参数 Datasheet PDF下载

CDK2000-CLK图片预览
型号: CDK2000-CLK
PDF下载: 下载PDF文件 查看货源
内容描述: 小数N分频时钟乘法器 [Fractional-N Clock Multiplier]
分类和应用: 时钟
文件页数/大小: 26 页 / 224 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2100-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
A
= -10°C to +70°C (Commercial Grade);
C
L
= 15 pF.
Parameters
Crystal Frequency
Fundamental Mode XTAL
Reference Clock Input Frequency
Symbol
f
XTAL
Conditions
RefClkDiv[1:0]
= 10
RefClkDiv[1:0]
= 01
RefClkDiv[1:0]
= 00
RefClkDiv[1:0]
= 10
RefClkDiv[1:0]
= 01
RefClkDiv[1:0]
= 00
Min
8
16
32
8
16
32
45
8
50 Hz
Typ
-
-
-
-
-
-
-
-
-
-
-
50
1.7
1.7
70
50
175
100
1
1
-
-
Max
18.75
37.5
50
18.75
37.5
75
55
18.75
30
-
-
75
55
3.0
3.0
-
-
-
200
3
3
±0.5
±112
Units
MHz
MHz
MHz
MHz
MHz
MHz
%
MHz
MHz
UI
ns
MHz
%
ns
ns
ps rms
ps rms
ps rms
UI
ms
ms
ppm
ppm
f
REF_CLK
Reference Clock Input Duty Cycle
Internal System Clock Frequency
Clock Input Frequency
Clock Input Pulse Width (Note
5)
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN (Note
9)
PLL Lock Time - REF_CLK
Output Frequency Synthesis Resolution (Note
10)
D
REF_CLK
f
SYS_CLK
f
CLK_IN
pw
CLK_IN
f
CLK_OUT
t
OD
t
OR
t
OF
t
JIT
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note
6)
(Notes
6, 7)
(Notes
6, 8)
t
LC
t
LR
f
err
f
CLK_IN
< 200 kHz
f
CLK_IN
> 200 kHz
f
REF_CLK
= 8 to 75 MHz
High Resolution
High Multiplication
f
CLK_IN
< f
SYS_CLK
/96
f
CLK_IN
> f
SYS_CLK
/96
2
10
6
45
-
-
-
-
-
-
-
-
0
0
Notes:
5. 1 UI (unit interval) corresponds to t
SYS_CLK
or 1/f
SYS_CLK
.
6.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points;
AuxOutSrc[1:0]
= 11.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9. 1 UI (unit interval) corresponds to t
CLK_IN
or 1/f
CLK_IN
.
10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS841F1
7