CS2300-CP
4. ARCHITECTURE OVERVIEW
4.1
Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2300 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu-
tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. The reference for the synthesizer is an on chip LC Oscillator (LCO) which
generates the necessary internal stable clocks. In very simplistic terms, the Fractional-N Frequency Syn-
thesizer multiplies the LC Oscillator by the value of N to generate the PLL output clock. The desired output
to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 4).
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock, the LCO, as a time
and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares
the fractional-N divided clock with the original timing reference and generates a control signal. The control
signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output fre-
quency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio
between the reference clock and the VCO output (thus the one’s density of the modulator sets the fractional
value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies
without the need for external filter components.
Phase
Comparator
Internal
Loop Filter
Voltage Controlled
Oscillator
LC Oscillator
PLL Output
Fractional-N
Divider
Delta-Sigma
Modulator
N
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer
4.2
Hybrid Analog-Digital Phase Locked Loop
The addition of the Digital PLL and Fractional-N Logic (shown in Figure 5) to the Fractional-N Frequency
Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical an-
alog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges
without the need to change external loop filter components while maintaining impressive jitter reduction per-
formance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the fre-
quency reference and compares that to the desired ratio. The digital logic generates a value of N which is
then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice
that the frequency and phase of the LCO does not affect the output of the PLL since the digital control loop
will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter
bandwidth can be altered. The PLL bandwidth is automatically set to a wide-bandwidth mode to quickly
achieve lock and then reduced for optimal jitter rejection.
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DS843PP1
CIRRUS [ CIRRUS LOGIC ]
