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CDB8422 参数 Datasheet PDF下载

CDB8422图片预览
型号: CDB8422
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192千赫,异步采样率转换器 [24-bit, 192 kHz, Asynchronous Sample Rate Converter with]
分类和应用: 转换器
文件页数/大小: 82 页 / 1416 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8422  
SORES1[1:0] - Resolution of the output data on SDOUT  
00 - 24-bit resolution.  
01 - 20-bit resolution.  
10 - 18-bit resolution.  
11 - 16-bit resolution  
SOFSEL1[1:0] - Format of the output data on SDOUT  
00 - Left-Justified  
01 - I²S  
10 - Right-Justified (Master mode only)  
11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits.  
The time slot occupied by the Z bit is used to indicate the location of the block start. Only valid if serial port  
sourced directly by the AES3-compatible receiver.  
TDM[1:0] - Enable the time-division multiplexing (TDM) through TDM_IN and either SDOUT1 or SDOUT2.  
See “Time Division Multiplexing (TDM) Mode” on page 27 for more details.  
00 - TDM Mode not enabled. Serial audio format selected by SOFSEL1[1:0]  
01 - TDM Mode enabled through TDM_IN and SDOUT1. SOFSEL1[1:0] has no effect in this mode.  
10 - TDM Mode enabled through TDM_IN and SDOUT2. SOFSEL2[1:0] has no effect in this mode.  
11 - Reserved  
11.13 Serial Audio Output Data Format - SDOUT2 (0Dh)  
7
SOMS2  
0
6
SOSF2  
0
5
4
3
2
1
0
SORES2_1  
0
SORES2_0  
0
SOFSEL2_1 SOFSEL2_0  
Reserved  
Reserved  
0
0
SOMS2 - Master/Slave Mode Selector  
0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.  
1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.  
SOSF2 - OSCLK2 Frequency. Valid only in master mode (SOMS2 = 1). If the SRC is selected as the source  
for SDOUT2 (SDOUT2[1:0] = 00 in register 0Ah), then the master clock (MCLK) is the SAO MCLK (as se-  
lected by the SAO_MCLK bit in register 08h). If the AES3 receiver is selected as the source for SDOUT2  
(SDOUT2[1:0] = 01 in register 0Ah), then the MCLK is RMCK. Should be changed when PDN = 1. See  
Table 10 for details. Note: If serial output 2 is in master mode and sourced directly by the serial input port,  
then SAI_CLK[3:0] determine the MCLK/OLRCK1 ratio.  
SAO_CLK[3:0],  
SAI_CLK[3:0], or  
RMCK[3:0]  
OSCLK2/OLRCK2 Ratio  
MCLK/OLRCK2 Ratio  
SOSF2 = 0  
SOSF2 = 1  
0000  
0001  
64  
96  
64  
48  
INVALID  
96  
Table 10. OSCLK2/OLRCK2 Ratios and SOSF1 Settings  
DS692PP1  
55