CDB53L21 参数 Datasheet PDF下载

CDB53L21

2.1

General Configuration Tab

The “General Configuration” tab provides high-level control of signal routing on the CDB53L21. This tab also

includes basic controls for the CS53L21 for quickly setting up the CDB53L21 in simple configurations. Sta-

tus text detailing the ADC’s specific configuration is shown in parenthesis or appears directly below the as-

sociated control. This text may change depending on the setting of the associated control. A description of

each control group is outlined below:

ADC Basic Configuration

- Includes basic register controls in the CS53L21 used for setting up the interface

format, clocking functions and internal analog input routing. See

through

for more

CS53L21 controls.

S/PDIF Transmitter Control

- Includes all available Hardware Mode controls for setting up the CS8406.

Clock/Data Routing and ADC Reset

- Includes controls used for routing clocks and data between the

CS53L21, oscillator and the I/O stake header. Also included is a reset control for the CS53L21.

Update -

Reads all registers in the FPGA and CS53L21 and reflects the current values in the GUI.

Reset

- Resets FPGA to default routing configuration.

Figure 1. General Configuration Tab

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DS700DB1