CDB5334/35/60
The evaluation board uses separate analog and dig-
ital ground planes which are joined together under-
neath resistors R6, R41, and R52-R55. This
arrangement isolates the analog circuitry from the
digital logic.
CDB5334/35/60 SYSTEM OVERVIEW
The CDB5334/35/60 evaluation boards are an ex-
cellent means of quickly evaluating the CS5334,
CS5335, or CS5360. The CS8402A digital audio
interface transmitter provides an easy interface to
digital audio signal processors, including the ma-
jority of digital audio test equipment. The evalua-
tion board has been designed to accept an analog
input, and provide optical and coaxial digital out-
puts. The evaluation board also allows the user to
access clocks and data through a 10-pin header for
system development. In addition, the evaluation
board supports the input level monitoring function
provided by the CS5334, CS5335, and CS5360.
The Peak Signal Level bits are displayed on bar-
graph LEDs or 7 segment displays for both left and
right channels.
Reset Circuit and Offset Calibration
Two methods of placing the CS5334, CS5335, or
CS5360 into power-down mode are provided on
the evaluation board. The CAL switch, shown in
Figure 8, pulls the DIF0 and DIF1 lines high on the
CS5334, CS5335, or CS5360, thus placing the
ADC into power-down mode. Releasing the CAL
switch causes the DIF0 and DIF1 settings to be re-
stored, upon which an initialization sequence be-
gins, as described in the CS5334/CS5335 and
CS5360 data sheets.
The reset circuit provided on the evaluation board
is shown in Figure 2. Upon power up, this circuit
sends a reset to the RST pin of the CS5334,
CS5335, or CS5360. Power-down, followed by
offset calibration, can also be performed by press-
ing and then releasing the RST switch. It should be
noted that only the RST method of powering down
the CS5334, CS5335, or CS5360 will include the
decision of master or slave operation.
The CDB5334/35/60 schematic has been parti-
tioned into 7 schematics shown in Figures 2
through 8. Each partitioned schematic is represent-
ed in the system diagram shown in Figure 1. Notice
that the system diagram also includes the connec-
tions between the partitioned schematics.
Power Supply Circuitry and Grounding
Power is supplied to the evaluation board by six
binding posts as shown in Figure 2. +5VA provides
5 Volt power to the converter and the reset circuit-
ry. The ±12 V binding posts provide power to the
analog input buffer. C1-C3 and C5-C7 provide
general power supply filtering for the analog sup-
plies. Z1-Z3 are transient suppression diodes which
also provide protection from incorrectly connected
power supply leads. +5VD supplies 5 Volt power
to the digital section of the board. C41 and C10 pro-
vide general power supply filtering. Z4 is a tran-
sient suppressor.
Input Buffer and Protection Circuits
The differential input circuit shown in Figure 3 is
well-suited for the CS5334, CS5335, and CS5360
in professional applications. The circuit will accept
a differential or single-ended signal of either polar-
ity and provide a differential signal with the proper
DC offset to the CS5334, CS5335, or CS5360. The
circuit also incorporates 6 dB of attenuation to
scale down professional input levels to the input
voltage range of the CS5334, CS5335, or CS5360.
A nominal input level of 4 Volts rms to the evalua-
tion board will achieve a full scale digital output
from the CS5334, CS5335, or CS5360. The com-
mon mode rejection of the system is limited by the
passive component matching of the input buffer
Localized decoupling for the CS5334, CS5335, or
CS5360 is provided by C16, C17, C32, and C33, as
shown in Figure 4. R10, C16, and C32 form a low
pass filter which isolates VA+ from noise on VD+.
2
DS194DB3
CIRRUS [ CIRRUS LOGIC ]
