CDB5321
Figures 5 and 6 illustrate the logic used to drive
connections at header JP6 (Rev. B Board) or J2
(Rev. C Board).
The Rev. C evaluation board can directly inter-
face to the CDBCAPTURE board through
connector J2. A D-type Flip-Flop must be added
in the patch area of the Rev. B evaluation board
to enable it to interface to the CDBCAPTURE
board. The CDBCAPTURE can be used to per-
form FFT analysis and noise histograms.
Tables 1 and 2 illustrate the DIP switch posi-
tions of switches S3 and S4. The switch
positions with asterisks indicate preferred set-
tin gs for driving the interface on the
CDBCAPTURE system.
The CS5322 filter should be set up for hardware
mode (H/S on switch S4 open). DIP switch S4
can then be used to select the desired output
word rate. After the selection on the DECA,
DECB, and DECC positions of the S4 DIP
switch, the S2 RESET switch must be activated,
10
+5 V
R4
+
10
µF
C5
+5
8
5
6
2
3
From
Figure 4
7
SCLK
SCLK
13
12
1
2
SOD
SOD
11
10
3
4
4
+5 10
+5
U10 74HC74
14
D
CL
1
Q
+5
5
12
D
13
Q
DRDYD
J2
+5V
+5V
DRDYD
SCLK
SOD
followed by the S1 SYNC switch (unless these
signals are controlled via the J1 and J3 header
signals).
Figure 7 illustrates the component layout of the
board while figures 8 and 9 illustrate the board
layout (not to scale).
Using the Evaluation Board
Connect the appropriate power supplies to the
binding posts of the board. Twist the +5V digi-
tal supply lead with the digital ground lead from
the board to the supply. Also twist the supply
leads for the analog voltages. Use a high quality
power supply which is low in noise and line fre-
quency(50/60 Hz) interference.
Power up the supplies. Then connect a coaxial
cable from the analog BNC to the signal source.
Note that the performance of the A/D converter
chip set will exceed the capability of most signal
generators, with respect to noise, distortion, and
line frequency interference.
DRDY
9
14
11 CL
U4 74HC04
Figure 6. Serial Latch Interface on CDB5321 (Rev C) board.
DS88DB2
21
CIRRUS [ CIRRUS LOGIC ]
