CS4812
tion code. This technique allows for real-time
control of all parameters specific to the application
code. Please refer to Figure 26 for the HostBoot
procedure flow chart and to Section 1.2.1 of
AN195 for an example of a host boot sequence.
SEND APPLICATION
SPECIFIC CONTROL PORT
CONFIG BYTES
WRITE BYTE 0XA4
TO CONTROL PORT
REGISTER 4 (MAP = 4)
3.7
Resets
There are several reset mechanisms in the CS4812
which affect different parts of the chip. Full chip re-
set can only be achieved by asserting the external
RST pin. With RST asserted, the chip enters low
power mode during which the control port, CO-
DEC and DSP are reset, all registers are returned to
their default values and the DAC outputs are mut-
ed. The RST pin should be asserted during power-
up until the power supplies have reached steady
state.
WRITE BYTE 0XA5
TO CONTROL PORT
REGISTER 4
WRITE BYTE 0XA7
TO CONTROL PORT
REGISTER 4
SEND 3 BYTE MESSAGE TO
THE DSP INPUT REGISTER
(MAP = 3) :0X000004
WAIT FOR REPLY FROM DSP
(REQ LINE GOES LOW)
If the supply voltage drops below 4 Volts, the CO-
DEC is reset, the DAC outputs are muted and the
DSP automatically executes a soft reset.
READ REPLY BYTE FROM DSP
OUTPUT REGISTER (MAP = 27)
Upon exit from a CODEC reset, the DSP restarts
the application code and the CODEC performs the
following procedure:
N
REPLY BYTE
= 0 01?
X
Y
– The CODEC resynchronizes.
– The DAC outputs unmute.
WRITE .LDT FILE INTO
DSP INPUT REGISTER (MAP = 16)
(LOAD APPLICATION CODE)
N
REQ
LOW?
Y
READ REPLY BYTE FROM DSP
OUTPUT REGISTER (MAP = 27)
N
REPLY BYTE
= 0 02?
X
Y
SEND 3 BYTE MESSAGE TO
THE DSP INPUT REGISTER
(MAP = 16):0X000005
WRITE BYTE 0XA6
TO CONTROL PORT
REGISTER 4
Figure 26. HostBoot Flow Diagram
DS291PP3
27
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