CS4812
2. TYPICAL CONNECTION DIAGRAMS
Ferrite Bead
+5 V
µ
1 F
µ
0.1 F
µ
F
µ
0.1 F
1
+
+
D
D
A
A
43 65
VD1..2
12
VA 1..3
18 88
86
87
7
AIN1L+
AIN1L-
AOUT1+
ANALOG
FILTER
ANALOG
FILTER
8
AOUT1-
90
91
9
AIN1R+
AIN1R-
AOUT2+
AOUT2-
ANALOG
FILTER
ANALOG
FILTER
10
92
14
15
16
17
20
21
22
23
57
CMOUT
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
To Optional
Input and
Output Buffers
µ
1 F
0.1 µF
A
A
CS4812
39
93
OVL
CMFILT+
CMFILT-
+
1µF
0.1 µF
94
RES-NC
RES-NC
A
58
59
60
VD VD
2.2
2.2
K
RES-NC
RES-NC
K
63
D
Q
SCL/CCLK
61
95
RES-NC
RES-NC
74HC74
62
68
67
71
47
Program ROM
or
Serial EEPROM
SDA/CDOUT
AD0/CS
Microcontroller
97
RES-NC
AD1/CDIN
REQ
VD
73
RES-VD
CLKOUT
RS
69
SPI/I2C
32
34
36
38
RES-DGND
RES-DGND
RES-DGND
RES-DGND
RES-DGND
70
SCPM/S
Mode/Reset
Circuit
D
72
RST
RESET
48
41
40
82
83
96
PIO0
PIO1
RES-DGND
RES-DGND
RES-DGND
Control/
Monitor
Circuitry
37
35
PIO2
PIO3
D
XTO
XTI
AGND1..4
1113 19 89
DGND1..4
66
44 64
46
42
45
Ω
1 M
Optional External
Clock Input instead
of Crystal
D
A
Ω
=33
R
S
All unused inputs
should be tied to ground.
39 pF 39 pF
D
D
Figure 5. Typical Connection Diagram, Control Port Slave Mode
14
DS291PP3
CIRRUS [ CIRRUS LOGIC ]
