CS43L43
5.11 MODE CONTROL 2 (ADDRESS 0BH)
7
MCLKDIV
0
6
5
4
3
2
DIF2
0
1
DIF1
0
0
DIF0
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
5.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 7
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
NOTE: Internal SCLK is not available when this function is enabled.
5.11.2 DIGITAL INTERFACE FORMAT (DIF) BIT 0-2
2
Default = 000 - Format 0 (I S, up to 24-bit data, 64 x Fs Internal SLCK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 2-4.
NOTE: Internal SCLK is not available when MCLKDIV is enabled.
DIF2
DIF1
DIF0
DESCRIPTION
I2S, up to 24-bit data, 64 x Fs Internal SLCK
I2S, up to 16-bit data, 32 x Fs Internal SLCK
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 1
Format
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
1
2
2
3
4
4
4
4
2
Table 14. Digital Interface Format - Control Port Mode
24
DS479PP3
CIRRUS [ CIRRUS LOGIC ]
