CS4329
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Symbol
Min
Typ
Max
Unit
Analog Output
Differential Full Scale Output Voltage
Output Common Mode Voltage
Differential Offset
(Note 5)
1.90
2.0
2.2
3
2.10
-
Vrms
V
-
-
15
-
mV
kΩ
pf
AC Load Resistance
R
C
4
-
-
L
Load Capacitance
-
100
L
Notes: 1. Triangular PDF Dithered Data
2. AUTO-MUTE active. See parameter definitions
3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz,
the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
4. Group Delay for Fs=48 kHz 25/48 kHz=520 µs
5. Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12.
SWITCHING CHARACTERISTICS (TA= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25
to 4.75 Volts; CL = 20 pF)
Parameter
MCLK / LRCK = 512
Symbol
Min
1
Typ
Max
Unit
kHz
ns
Input Sample Rate
Fs
-
-
-
-
-
-
-
50
-
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
10
10
21
21
31
32
MCLK / LRCK = 512
MCLK / LRCK = 384
MCLK / LRCK = 384
MCLK / LRCK = 256
MCLK / LRCK = 256
-
ns
-
ns
-
ns
-
ns
-
ns
t
20
20
-
-
-
-
-
-
ns
ns
ns
sclkl
t
t
sclkh
1
sclkw
-------------------
128(Fs)
SCLK rising to LRCK edge delay
t
20
-
-
-
-
-
-
-
-
ns
ns
ns
ns
slrd
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
t
20
slrs
t
20
sdlrs
t
20
sdh
1
SCLK Period
SCLK / LRCK = 64
t
-
-
-
-
-
-
-
-
ns
ns
ns
ns
sclkw
----------------
64(Fs)
1
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512
SCLK rising to SDATA hold time MCLK / LRCK = 384
t
sdlrs
-------------------
+ 10
512(Fs)
t
1
sdh
-------------------
+ 15
+ 15
512(Fs)
t
1
sdh
-------------------
384(Fs)
DS153F1
3
CIRRUS [ CIRRUS LOGIC ]
