CS43122
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25° C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
2 Wire Mode
SCL Clock Frequency
fscl
tirs
-
100
KHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
RST Rising Edge to Start
500
4.7
4.0
4.7
4.0
4.7
0
-
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
tr
-
-
-
Clock High Time
-
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
-
(Note 8)
-
250
-
-
1
tf
-
300
-
tsusp
4.7
Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
irs
Repeated
Stop
Start
Stop
Start
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
low
hdd
Figure 2. 2 Wire Mode Control Port Timing
10
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