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CDB4207 参数 Datasheet PDF下载

CDB4207图片预览
型号: CDB4207
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗, 4入/ 6出的HD音频编解码器与耳机放大器 [Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp]
分类和应用: 解码器编解码器放大器
文件页数/大小: 144 页 / 782 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4207
Digital Audio Interface Receiver
Complete EIAJ CP1201, IEC-60958, S/PDIF
General Description
The CS4207 is a highly integrated multi-channel low-
power HD Audio CODEC featuring 192 kHz DACs,
96 kHz ADCs, 192 kHz S/PDIF Transmitters and Re-
ceiver, Microphone pre-amp and bias voltage, and a
ground centered Headphone driver. Based on multi-bit,
delta-sigma modulation, it allows infinite sample rate
adjustment between 32 kHz and 192 kHz.
The ADC input path allows control of a number of fea-
tures. The microphone input path includes a selectable
programmable-gain pre-amplifier stage and a low-noise
MIC bias voltage supply. A PGA is available for line and
microphone inputs and provides analog gain with soft
ramp and zero cross transitions. The ADC also features
an additional digital volume attenuator with soft ramp
transitions.
The stereo headphone amplifier is powered from a sep-
arate internally generated positive supply, with an
integrated charge pump providing a negative supply.
This allows a ground-centered analog output with a
wide signal swing and eliminates external DC-blocking
capacitors.
The integrated digital audio interface receiver and trans-
mitters utilize a 24-bit, high-performance, monolithic
CMOS stereo asynchronous sample rate converter to
clock align the PCM samples to/from the S/PDIF inter-
faces. Auto detection of non-PCM encoded data
disables the sample rate conversion to preserve bit ac-
curacy of the data.
In addition to its many features, the CS4207 operates
from a low-voltage analog and digital core, making this
part ideal for portable systems that require low power
consumption in a minimal amount of space.
The CS4207 is available in a 48-pin WQFN package in
both Automotive (-40°C to +105°C) and Commercial (-
40°C to +85°C) grades. The CS4207 Customer Demon-
stration board is also available for device evaluation and
implementation suggestions. Please refer to
for complete ordering
information.
Compatible Receiver
32 kHz to 192 kHz Sample Rate Range
Automatic Detection of Compressed Audio
Streams
Integrated Sample Rate Converter
128 dB Dynamic Range
-120 dB THD+N
Supports Sample Rates up to 192 kHz
1:1 Input/Output Sample Rate Ratios
Digital Audio Interface Transmitters
Two Independent EIAJ CP1201, IEC-60958,
S/PDIF Compatible Transmitters
32 kHz to 192 kHz Sample Rate Range
System Features
Very Low D3 Power Dissipation of <7 mW
Jack Detect Active in D3
HDA Bus BITCLK not required for D3 State
Jack Detect Does not Require HDA Bus
BITCLK
All Configuration Settings are Preserved in D3
State
Pop/Click Suppression in State Transitions
Detects Wake Event and Generates Power
State Change Request when HDA Bus
Controller is in D3
Variable Power Supplies
– 1.5 V to 1.8 V Digital Core Voltage
– 3.3 V to 5.0 V Analog Core Voltage
– 3.3 V to 5.0 V Headphone Drivers
– 1.5 V to 3.3 V HD Bus Interface Logic
– 3.3 V Interface Logic levels for GPIO,
S/PDIF, and Digital Mic.
Individual Power-down Managed
ADCs, DACs, PGAs, Headphone Driver,
S/PDIF Receiver, and Transmitters
2
DS880F1