CS4222
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25°C VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30pF)
Parameter
Symbol
Min
Max
6
-
-
-
-
-
-
-
-
100
100
Units
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
SPI Mode
(SPI/I
2
C = 0)
CCLK Clock Frequency
f
sck
-
RST rising edge to CS falling
t
srs
500
CCLK edge to CS falling
(Note 9)
t
spi
500
CS High Time Between Transmissions
t
csh
1.0
CS Falling to CCLK Edge
t
css
20
CCLK Low Time
t
scl
66
CCLK High Time
t
sch
66
CDIN to CCLK Rising Setup Time
t
dsu
40
CCLK Rising to DATA Hold Time
(Note 10)
t
dh
15
Rise Time of CCLK and CDIN
(Note 11)
t
r2
-
Fall Time of CCLK and CDIN
(Note 11)
t
f2
-
Notes: 9. t
spi
only needed before first falling edge of CS after RST rising edge.
t
spi
= 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For F
SCK
< 1 MHz
RST
t srs
CS
t spi t css
CCLK
t r2
CDIN
t scl
t
sch
t
csh
t f2
t dsu t
dh
DS236PP3
5
CIRRUS [ CIRRUS LOGIC ]
