CS5102A
ANALOG CHARACTERISTICS
Parameter*
Specified Temperature Range
(continued)
CS5102A -J,K
CS5102A -A,B
CS5102A -S,T
°C
ns
ps
pF
pF
Symbol Min Typ Max Min Typ Max Min Typ Max Units
-
-
-
-
-
-
-
0 to +70
30
100
320
200
-
-
425
265
-
-
-
-
40 to +85
30
100
320
200
-
-
425
265
-55 to +125
-
-
-
-
30
100
320
200
-
-
425
265
Analog Input
Aperture Time
Aperture Jitter
Input Capacitance
(Note 6)
Unipolar Mode
Bipolar Mode
(Note 19)
(Note 20)
(Note 21)
-
-
Conversion & Throughput
Conversion Time
Acquisition Time
Throughput
t
c
t
a
f
tp
-
-
20
-
-
-
40.625
9.375
-
-
-
20
-
-
-
40.625
9.375
-
-
-
20
-
-
-
40.625
9.375
-
µs
µs
kHz
Power Supplies
Power Supply Current
(Note 22)
Positive Analog
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital
Power Consumption
(Notes 11, 22)
(SLEEP High)
(SLEEP Low)
I
A
+
I
A
-
I
D
+
I
D
-
P
do
P
ds
PSR
PSR
-
-
-
-
-
-
-
-
2.4
-2.4
2.5
-1.5
44
1
84
84
3.5
-3.5
3.5
-2.5
65
-
-
-
-
-
-
-
-
-
-
-
2.4
-2.4
2.5
-1.5
44
1
84
84
3.5
-3.5
3.5
-2.5
65
-
-
-
-
-
-
-
-
-
-
-
2.4
-2.4
2.5
-1.5
44
1
84
84
3.5
-3.5
3.5
-2.5
65
-
-
-
mA
mA
mA
mA
mW
mW
dB
dB
Power Supply Rejection:
(Note 23)
Positive Supplies
Negative Supplies
Notes: 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,
internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling
edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will
not exceed 1 master clock cycle + 140 ns.
20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625
µs
of fine charge.
FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625
µs
with an 1.6 MHz
clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may
be less than 9 clock cycles.
21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions
affecting acquisition and conversion times, as described above.
22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.
23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply
rejection versus frequency.
Typ. Power (mW) CLKIN (MHz)
34
0.8
37
1.0
39
1.2
41
1.4
44
1.6
6
DS45F2
CIRRUS [ CIRRUS LOGIC ]
