CS5012A, CS5014, CS5016
SWITCHING CHARACTERISTICS (T = T
to T ; VA+, VD+ = 5V ±10%;
MAX
A
MIN
VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF, BW = VD+)
L
Parameter
CS5012A CLKIN Frequency:
Symbol
Min
Typ
Max
Units
f
CLK
CLK
Internally Generated:
Externally Supplied:
1.75
100 kHz
100 kHz
-
-
-
-
MHz
MHz
MHz
-7
-12
6.4
4.0
CS5014/5016 CLKIN Frequency:
f
Internally Generated:
-14, -16
-28, -32
-14, -16
-28, -32
1.75
1
100 kHz
100 kHz
-
-
-
-
-
-
4
2
MHz
MHz
MHz
MHz
Externally Supplied:
CLKIN Duty Cycle
Rise Times:
40
-
60
%
Any Digital Input
Any Digital Output
t
-
-
-
20
1.0
-
µs
ns
rise
Fall Times:
Any Digital Input
Any Digital Output
t
fall
-
-
-
20
1.0
-
µs
ns
HOLD Pulse Width
Conversion Time:
t
1/f
+50
-
t
c
ns
hpw
CLK
CS5012A
CS5014
CS5016
t
c
49/f
57/f
65/f
+50
CLK
-
-
-
53/f
61/f
69/f
+235 ns
+235 ns
+235 ns
CLK
CLK
CLK
CLK
CLK
Data Delay Time
EOC Pulse Width
Set Up Times:
t
-
40
-
100
-
ns
ns
dd
(Note 11)
t
4/f
-20
CLK
epw
CAL, INTRLV to CS Low
A0 to CS and RD Low
t
t
20
20
10
10
-
-
ns
ns
cs
as
Hold Times:
CS or RD High to A0 Invalid
CS High to CAL, INTRLV Invalid
t
t
50
50
30
30
-
-
ns
ns
ah
ch
Access Times:
CS Low to Data Valid
A, B, J, K
t
-
-
-
-
90
115
90
120
150
120
150
ns
ns
ns
ns
ca
S, T
A, B, J, K
S, T
RD Low to Data Valid
t
ra
90
Output Float Delay:
Serial Clock
K, B
t
-
-
90
90
110
140
ns
ns
fd
CS or RD High to Output Hi-Z
T
Pulse Width Low
Pulse Width High
t
-
-
2/f
-
-
ns
ns
pwl
CLK
CLK
t
2/f
2/f
2/f
pwh
Set Up Times:
Hold Times:
SDATA to SCLK Rising
SCLK Rising to SDATA
t
2/f
-50
-
-
ns
ns
ss
sh
CLK
CLK
CLK
t
2/f
-100
CLK
Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
2-14
DS14F6
CIRRUS [ CIRRUS LOGIC ]
