欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS8126-1YTHE5 参数 Datasheet PDF下载

CS8126-1YTHE5图片预览
型号: CS8126-1YTHE5
PDF下载: 下载PDF文件 查看货源
内容描述: 5V , 750毫安低压差线性稳压器,具有延时复归 [5V, 750mA Low Dropout Linear Regulator with Delayed RESET]
分类和应用: 线性稳压器IC调节器电源电路输出元件局域网
文件页数/大小: 9 页 / 210 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
 浏览型号CS8126-1YTHE5的Datasheet PDF文件第1页浏览型号CS8126-1YTHE5的Datasheet PDF文件第2页浏览型号CS8126-1YTHE5的Datasheet PDF文件第3页浏览型号CS8126-1YTHE5的Datasheet PDF文件第4页浏览型号CS8126-1YTHE5的Datasheet PDF文件第6页浏览型号CS8126-1YTHE5的Datasheet PDF文件第7页浏览型号CS8126-1YTHE5的Datasheet PDF文件第8页浏览型号CS8126-1YTHE5的Datasheet PDF文件第9页  
CS8126, -1, -2
RESET Circuit Waveform
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
V
OUT
V
RT(ON)
V
RT(OFF)
V
RH
RESET
(1)
(2)
V
RL
(3)
t
Delay
Delay
V
DH
V
DC(HI)
V
DC(LO)
(2)
V
DIS
Circuit Description
The CS8126 RESET function, has hysteresis on both the
Reset and Delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when the output
voltage falls below V
RT(OFF)
, causes the RESET output tran-
sistor to be in the ON (saturation) state. When the output
voltage rises above V
RT(ON)
, this circuit permits the RESET
output transistor to go into the OFF state if allowed by
the RESET Delay circuit.
RESET Delay Circuit
This circuit provides a programmable (by external capaci-
tor) delay on the RESET output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above V
RT(ON)
. Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage falls below V
RT(OFF)
. The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled RESET pulse is generated following
detection of an error condition. The circuit allows
the RESET output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
V
DC(H1)
.
The Delay time for the RESET function is calculated from
the formula:
C
Delay
´
V
Delay
Threshold
Delay time =
I
Charge
Delay time = C
Delay
´
3.2
´
10
5
If C
Delay
= 0.1µF, Delay time (ms) = 32ms ± 50%: i.e. 16ms
to 48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
5