RESET Circuit Waveform
V
OUT
V
RH
V
RT(ON)
V
RT(OFF)
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
(1)
RESET
(2)
(3)
V
RL
t
Delay
Delay
V
DH
V
DC(HI)
V
DC(LO)
V
DIS
(2)
Circuit Description
function, has hysteresis on both the
RESET
Reset Delay Circuit
The CS8122
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The Reset Delay Circuit provides a programmable (by
RESET
external capacitor) delay on the
output lead. The
RESET
The
circuit output is an open collector type with
RESET
Delay lead provides source current to the external delay
capacitor only when the Low Voltage Inhibit circuit indi-
cates that output voltage is above VRT(ON). Otherwise, the
Delay lead sinks current to ground (used to discharge the
delay capacitor). The discharge current is latched ON
when the output voltage is below VRT(OFF). The Delay
capacitor is fully discharged anytime the output voltage
falls out of regulation, even for a short period of time. This
ON and OFF parameters as specified. The
output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
The Low Voltage Inhibit Circuit monitors output voltage,
and when output voltage is below the specified minimum,
RESET
feature ensures that a controlled
following detection of an error condition. The circuit
RESET
pulse is generated
RESET
causes the
ration) state. When the output voltage is above the speci-
RESET
output transistor to be in the ON (satu-
allows the
state only when the voltage on the Delay lead is higher
than VDC(HI)
output transistor to go to the OFF (open)
fied level, this circuit permits the
output transistor
RESET
to go into the OFF state if allowed by the
cuit.
Delay cir-
.
Test Circuit
VOUT
VIN
C
*
IN
100nF
C
**
OUT
RRST
4.7kW
10mF
CS8122
Delay
RESET
Gnd
C
Delay
0.1mF
*CIN required if regulator is far from power source filter.
**COUT required for stability.
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
