CS8120
Circuit Description: continued
If the input voltage rises above 26V (e.g. load dump), the
output shuts down. This response protects the internal cir-
cuitry and enables the IC to survive unexpected voltage
transients.
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
Should the junction temperature of the power device
exceed 180ûC (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
Regulator Control Functions
The CS8120 contains two microprocessor compatible con-
trol functions: ENABLE and RESET (Figure 3).
ENABLE
Function
ENABLE switches the output transistor. When the voltage
on the ENABLE lead exceeds 2.9V typ, the output pass
transistor turns off, leaving a high impedance facing the
load. The IC will remain in Sleep mode, drawing only
250µA, until the voltage on the lead drops below 2.1V typ.
Hysteresis (800mV) is built into the ENABLE function to
FOR 7V < V
IN
< 26V
provide good noise immunity.
RESET
Function
A RESET signal (low voltage) is generated as the IC pow-
ers up (V
OUT
> V
OUT
- 100mV) or when V
OUT
drops out of
regulation (V
OUT
< V
OUT
- 140mV, typ). 40mV of hysteresis
is included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
V
OUT
C
2
22mF
5V to
mP
and
System
Power
CS–8120
RESET
R
RST
to
mP
RESET
Port
C
RST
Figure 4: RC Network for RESET Delay circuitry
V
IN
guaranteeing that the RESET signal is valid for V
OUT
as low
as 1V.
An external RC network on the RESET lead (Figure 4) pro-
vides a sufficiently long delay for most microprocessor
based applications. RC values can be chosen using the fol-
lowing formula:
R
TOT
´
C
RST
ENABLE
HI
V
IN(HI)
LO
V
RT(ON)
V
RT(OFF)
[
Ðt
Delay
ln
where:
(1)
(
V
T
Ð V
OUT
V
RST
Ð V
OUT
)
]
V
OUT
VR
H
PEAK
(2)
VR
SAT
VR
PEAK
R
TOT
= R
RST
in parallel with R
IN,
R
IN
= µP port impedance,
C
RST
= RESET delay capacitor,
t
Delay
= desired delay time,
V
RST
= V
SAT
of RESET lead
(0.7V @ turn - on), and
V
T
= µP logic threshold voltage.
RESET
(1) = NO RESET DELAY CAPACITOR
(2) = WITH RESET DELAY CAPACITOR
Figure 3: Circuit Waveforms for CS8120
Applications Notes
The circuit depicted in Figure 5 lets the microprocessor
control its power source, the CS8120 regulator. An I/O
port on the µP and the SWITCH port are used to drive the
base of Q1. When Q1 is driven into saturation, the voltage
on the ENABLE lead falls below its lower threshold. The
regulatorÕs output is switched out. When the drive cur-
rent is removed, the voltage on the ENABLE lead rises,
the output is switched off and the IC moves into Sleep
mode where it draws 250µA.
By coupling these two controls with ENABLE , the system
has added flexibility. Once the system is running, the
state of the SWITCH is irrelevant as long as the I/O port
continues to drive Q1. The µP can turn off its own power
5
by withdrawing drive current, once the SWITCH is open.
This software control at the I/O port allows the µP to fin-
ish key housekeeping functions before power is removed.
The logic options are summarized in Table 1 below
Table 1: Logic Control of CS8120 Output
µP I/O drive
SWITCH ENABLE
Output
ON
OFF
Closed
Open
Closed
Open
LOW
LOW
LOW
HIGH
ON
ON
ON
OFF
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
