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CS8101YDWFR20 参数 Datasheet PDF下载

CS8101YDWFR20图片预览
型号: CS8101YDWFR20
PDF下载: 下载PDF文件 查看货源
内容描述: 微5V , 100mA时的低压差线性稳压器,带有复位和使能 [Micropower 5V, 100mA Low Dropout Linear Regulator with RESET and ENABLE]
分类和应用: 稳压器调节器光电二极管输出元件
文件页数/大小: 8 页 / 200 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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CS8101
Circuit Description: continued
based applications. RC values can be chosen using the
following formula:
V
OUT
C
OUT
5V to
mP
and
System
Power
R
TOT
C
RST
=
CS8101
RESET
R
RST
[
(
ln
Ðt
Delay
V
T
Ð V
OUT
V
RST
Ð V
OUT
)
]
to
mP
RESET
Port
C
RST
where:
R
RST
= RESET Delay resistor
R
IN
= µP port impedance
R
TOT
= R
RST
in parallel with R
IN
C
RST
= RESET Delay capacitor
Figure 3. RC Network for RESET Delay
t
Delay
= desired delay time
V
RST
= V
SAT
of RESET lead (0.7V @ turn - ON)
V
T
= RESET threshold
An external RC network on the RESET lead (Figure 3) pro-
vides a sufficiently long delay for most microprocessor
Applications Notes
V
BAT
0.1mF
500kW
V
IN
V
OUT
V
CC
CS8101
ENABLE
RESET
R
RST
C
OUT
mP
Gnd
RESET
C
RST
I/O Port
Q
1
100kW
500kW
100kW
SWITCH
Figure 4. Microprocessor Control of CS8101 using external switching transistor Q
1
.
The circuit depicted in Figure 4 lets the microprocessor
control its power source, the CS8101 regulator. An I/O
port on the µP and the SWITCH port are used to drive the
base of Q1. When Q1 is driven into saturation, the voltage
on the ENABLE lead falls below its lower threshold. The
regulatorÕs output is enabled. When the drive current is
removed, the voltage on the ENABLE lead rises, the out-
put is switched off and the IC moves into Sleep mode
where it draws 50µA (max).
By coupling these two controls with the ENABLE lead, the
system has added flexibility. Once the system is running,
the state of the SWITCH is irrelevant as long as the I/O
port continues to drive Q1. The microprocessor can turn
off its own power by withdrawing drive current, once the
SWITCH is open. This software control at the I/O port
allows the microprocessor to finish key housekeeping
functions before power is removed.
The logic options are summarized in Table 1.
4