CS52843
Circuit Description
When the power supply sees a sudden large output cur-
rent increase, the control voltage will increase allowing the
duty cycle to momentarily increase. Since the duty cycle
tends to exceed the maximum allowed to prevent trans-
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
V
OSC
OSC
RESET
Toggle
F/F Output
EA Output
Switch
Current
V
CC
Setting the Oscillator
The times T
c
and T
d
can be determined as follows:
t
c
= R
T
C
T
ln
t
d
= R
T
C
T
ln
(
(
V
REF
- V
LOWER
V
REF
- V
UPPER
)
)
V
REF
- I
d
R
T
- V
LOWER
V
REF
- I
d
R
T
- V
UPPER
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
UPPER
= 2.7V, V
LOWER
= 1.0V, I
d
= 8.3mA,
then
t
c
≈
0.5534R
T
C
T
I
O
t
d
= R
T
C
T
ln
V
O
(
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
)
Figure 2: Timing Diagram
For better accuracy R
T
should be
≥10kΩ.
Grounding
V
REF
R
T
OSC
C
T
Gnd
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
V
upper
V
lower
t
c
t
d
Sawtooth Mode
LARGE R
T
(≈10kΩ)
V
OSC
Internal Clock
Triangular Mode
SMALL R
T
(≈700kΩ)
V
REF
Internal Clock
Figure 3: Oscillator Timing Network and Parameters
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
