欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS5166 参数 Datasheet PDF下载

CS5166图片预览
型号: CS5166
PDF下载: 下载PDF文件 查看货源
内容描述: 5位同步CPU控制器与电源就绪和电流限制 [5-Bit Synchronous CPU Controller with Power-Good and Current Limit]
分类和应用: 控制器
文件页数/大小: 22 页 / 436 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
 浏览型号CS5166的Datasheet PDF文件第7页浏览型号CS5166的Datasheet PDF文件第8页浏览型号CS5166的Datasheet PDF文件第9页浏览型号CS5166的Datasheet PDF文件第10页浏览型号CS5166的Datasheet PDF文件第12页浏览型号CS5166的Datasheet PDF文件第13页浏览型号CS5166的Datasheet PDF文件第14页浏览型号CS5166的Datasheet PDF文件第15页  
Application Information: continued  
and provided that PWRGD is low. It is also required that  
V
CORE  
R1  
the overvoltage condition be present for at least the  
PWRGD delay time for the OVP signal to be activated. The  
resistor values shown in Figure 15 are for VDAC = +2.8V  
(DAC = 10111). The VOVP (overvoltage trip-point) can be  
set using the following equation:  
15K  
56K  
Q3  
2N3906  
+5V  
R2  
5K  
R2  
R1  
OVP  
VOVP = VBEQ3 1 +  
20K  
10K  
+5V  
(
)
10K  
Q2  
2N3904  
CS5166  
10K  
Q1  
2N3906  
PWRGD  
Figure 15: Circuit to implement a dedicated OVP output using the  
CS5166.  
Power-Good Circuit  
The Power-Good pin (pin 13) is an open-collector signal  
consistent with TTL DC specifications. It is externally  
pulled -up, and is pulled low (below 0.3V) when the regu-  
lator output voltage typically exceeds ± 8.5% of the nomi-  
nal output voltage. Maximum output voltage deviation  
before Power-Good is pulled low is ± 12%.  
Trace 4 = 5V from PC Power Supply (5V/div.)  
Trace1 = Regulator Output Voltage (1V/div.)  
Trace 2 = Inductor Switching Node (5V/div.)  
Figure 13: OVP response to an input-to-output short circuit by immedi-  
ately providing 0% duty cycle, crow-barring the input voltage to  
ground.  
2.825V  
Trace 2 - PWRGD (2V/div)  
Trace 4 - V  
(1V/div)  
OUT  
Figure 16: PWRGD signal becomes logic high as VOUT enters -8.5% of  
lower PWRGD threshold, VOUT = +2.825V (DAC = 10111).  
Trace 4 = 5V from PC Power Supply (2V/div.)  
Trace 1 = Regulator Output Voltage (1V/div.)  
Figure 14: OVP response to an input-to-output short circuit by pulling  
the input voltage to ground.  
Trace 1 PWRGD (2V/div)  
Trace 4 V (1V/div)  
FB  
Figure 17: Power-Good response to an out of regulation condition.  
11