Application Information: continued
Trace 2 - PWRGD (2V/div)
Trace 4 - V (1V/div)
OUT
Trace 1 PWRGD (2V/div)
Trace 4 V (1V/div)
FB
Figure 15: PWRGD signal becomes logic high as VOUT enters -8.5% of
lower PWRGD threshold, VOUT = +2.84V (DAC = 10111)
Figure 17: Power Good is insensitive to out of regulation conditions
that are present for a duration less than the built in delay.
Selecting External Components
The CS5165H buck regulator can be used with a wide
range of external power components to optimize the cost
and performance of a particular design. The following
information can be used as general guidelines to assist in
their selection.
NFET Power Transistors
Both logic level and standard FETs can be used. The refer-
ence designs derive gate drive from the 12V supply which
is generally available in most computer systems and utilize
logic level FETs. A charge pump may be easily implement-
ed to permit use of standard FET’s or support 5V or 12V
only systems (maximum of 20V). Multiple FET’s may be
paralleled to reduce losses and improve efficiency and
thermal management.
Trace 1 PWRGD (2V/div)
Trace 4 V (1V/div)
FB
Figure 16: Power Good response to an out of regulation condition.
Voltage applied to the FET gates depends on the applica-
tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail to rail due to overshoot caused by the capacitive
load they present to the controller IC. For the typical appli-
cation where VCC = 12V and 5V is used as the source for
the regulator output current, the following gate drive is
provided:
Figure 16 shows the relationship between the regulated
output voltage VFB and the Power Good signal. To prevent
Power Good from interrupting the CPU unnecessarily, the
CS5165H has a built-in delay to prevent noise at the VFB
pin from toggling Power Good. The internal time delay is
designed to take about 75µs for Power Good to go low and
65µs for it to recover. This allows the Power Good signal to
be completely insensitive to out of regulation conditions
that are present for a duration less than the built in delay
(see figure 17).
VGS (TOP) = 12V - 5V = 7V, VGS(BOTTOM) = 12V (see Figure 18).
It is therefore required that the output voltage attains an
out of regulation or in regulation level for at least the built-
in delay time duration before the Power Good signal can
change state.
12
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
