Applications Information: continued
5V
R3
Power Good
PN3904
10k
R1
10k
PN3904
VOUT
CS5157
R2
6.2k
Figure 15: Implementing Power Good with the CS5157.
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Figure 13: OVP response to an input-to-output short circuit by pulling
the input voltage to ground.
External Output Enable Circuit
Ch 1 High
2.80V
On/off control of the regulator can be implemented
through the addition of two additional discrete compo-
nents (see Figure 14). This circuit operates by pulling the
soft start pin high, and the VFFB pin low, emulating a short
circuit condition.
5V
Trace 3 = 12V Input (V
) and V
CC1
) (10V/div.)
CC2
Trace 4 = 5V Input (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Trace 2 = Power Good Signal (2V/div.)
MMUN2111T1 (SOT-23)
5
Figure 16: CS5157 demonstration board during power up. Power Good
signal is activated when output voltage reaches 1.70V.
SS
CS5157
8
Selecting External Components
VFFB
IN4148
The CS5157 can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.
Shutdown
Input
Figure 14: Implementing shutdown with the CS5157.
NFET Power Transistors
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and ther-
mal management.
External Power Good Circuit
An optional Power Good signal can be generated through
the use of four additional external components (see Figure
15). The threshold voltage of the Power Good signal can be
adjusted per the following equation:
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5V of ground
when in the low state and to within 2V of their respective
bias supplies when in the high state. In practice, the MOS-
FET gates will be driven rail to rail due to overshoot caused
by the capacitive load they present to the controller IC. For
the typical application where VCC1 = VCC2 = 12V and 5V is
(R1 + R2) × 0.65V
VPower Good
=
R2
This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages
less than VPower Good
.
10
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
