CS5151
Block Diagram
V
CC2
V
CC1
-
+
3.90V
3.85V
V
CC1
Monitor
Comparator
5V
-
60µA
0.7V
+
SS Low
Comparator
R
S
Q
Q
V
GATE
FAULT
FAULT
PGnd
SS
2µA
+
-
SS High
Comparator
FAULT
Latch
V
ID0
V
ID1
V
ID2
V
ID3
4 BIT
DAC
+
-
Error
Amplifier
2.5V
PWM
Comparator
-
GATE = ON
GATE = OFF
C
OFF
One Shot
R
S
Q
V
FB
COMP
V
FFB
Slow Feedback
+
Maximum
On-Time
Timeout
Normal
Off-Time
Timeout
R
S
Q
Q
PWM
Latch
Fast Feedback
-
+
Extended
Off-Time
Timeout
V
FFB
Low
Comparator
Off-Time
Timeout
C
OFF
LGnd
1V
PWM
COMP
Time Out
Timer
(30µs)
Edge Triggered
Applications Information
Theory of Operation
V
2
™ Control Method
The V
2
™ method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
PWM
Comparator
+
C
–
Ramp
Signal
COMP
Error
Signal
V
GATE
V
FFB
Output
Voltage
Feedback
V
FB
–
The V
2
™ control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
™
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
™ control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
5
Error
Amplifier
E
+
Reference
Voltage
Figure 1: V
2
™ Control Diagram
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
