CS5132
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
14
13
12
11
10
9
7
6
5
C
OFF2
COMP2
V
OUT2
V
FB2
V
FFB2
LGnd
V
FB1
V
OUT1
COMP1
4
8
C
OFF1
V
FFB1
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets the off
time for the non-synchronous regulator (V
I/O
).
V
I/O
section error amp output. PWM comparator inverting input. A
capacitor to LGnd provides error amp compensation.
V
I/O
section current limit comparator inverting input.
V
I/O
section error amp inverting feedback input.
V
I/O
PWM comparator fast feedback non-inverting input. V
I/O
sec-
tion current limit comparator non-inverting input.
Logic ground.
V
CORE
section error amp inverting input, PWRGD and OVP compara-
tor input.
V
CORE
section current limit comparator inverting input.
V
CORE
section error amp output.
V
CORE
section PWM comparator
inverting input. A capacitor to LGnd provides error amp compensa-
tion.
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets the off
time for the synchronous regulator (
V
CORE
).
V
CORE
section PWM comparator fast feedback non-inverting input.
V
CORE
section current limit comparator non-inverting input.
Block Diagram
V
FFB1
COMP1
C
OFF1
PWM
COMP1
V
CC1
V
CC2
- +
+
-
+
+
EA1
-
UVLO
V
FB1
1.06V
Current
Limit1
-
+
+
-
0.25V
Discharge
Comparator
R
Q
Fault
Latch1
Off Time1
One Shot
PGnd
Non-overlap
Logic
GATE(H)
86mV
V
OUT1
VID0
VID1
VID2
VID3
VID4
- +
-
DAC
S
PGnd
GATE(L)
C
OFF2
PWM
COMP2
GATE
+
1.10V
-
+ -
-
+
Off Time2
One Shot
PGnd
V
FFB2
V
FB2
-
+
-
+
PWRGD
V
CC1
OVP
-
86mV
+
-
1.23V
EA2
+
+
-
0.25V
Discharge
Comparator
-
Current
Limit2
+
+ -
Q
Fault
Latch2
R
V
OUT2
S
COMP2
LGnd
PGnd
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
