Application Information: continued
Adding slope compensation to the control loop, avoids
Protection and Monitoring Features
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switch-
point.
The scheme that prevents that switching noise prematurely
triggers the PWM circuit consists of adding a positive volt-
age slope to the output of the Error Amplifier (COMP pin)
during an off-time cycle.
Over-Current Protection
A loss-less hiccup mode current limit protection feature is
provided, requiring only the COMP capacitor to imple-
ment. The CS5132 provides overcurrent protection by sens-
ing the current through a ÒDroopÓ resistor, using an inter-
nal current sense comparator. The comparator compares
the voltage drop across the ÒDroopÓ resistor to an internal
reference voltage of 86mV (typical).
If the voltage drop across the ÒDroopÓ resistor exceeds this
threshold, the current sense comparator allows the fault
latch to be set. This causes the regulator to stop switching.
The circuit that implements this function for the syn-
chronous regulator section (VCC(CORE)) is shown in Figure 6.
5
COMP1
During this over current condition, the CS5132 stays off for
the time it takes the COMP pin capacitor to discharge to its
lower 0.25V threshold. As soon as the COMP pin reaches
0.25V, the Fault latch is reset (no overcurrent condition pre-
sent) and the COMP pin is charged with a 30µA current
source to a voltage 1.06V greater than the VFFB voltage.
Only at this point the regulator attempts to restart normal-
ly. The CS5132 will operate initially with a duty cycle
whose value depends on how low the VFFB voltage was
during the overcurrent condition (whether hiccup mode
was due to excessive current or hard short). This protection
scheme minimizes thermal stress to the regulator compo-
nents, input power supply, and PC board traces, as the over
current condition persists. Upon removal of the overload,
the fault latch is cleared, allowing normal operation to
resume.
C
2
COMP
CS5132
R
C
1
R
1
19
GATE(L)
To Synchronous FET
Figure 6: Small RC filter provides the proper voltage ramp at the begin-
ning of each on-time cycle.
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on-time cycle. The resistors R1 and R2 in the circuit of
Figure 6 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier.
A similar approach can be used also for the non-syn-
chronous regulator section (VI/O) as shown in Figure 7. In
this case, the slope compensation signal is generated direct-
ly from the GATE output, through the ac coupling capaci-
tor C1, at the beginning of each on-cycle.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V2TM control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 200ns, causing
the top MOSFET to shut off, disconnecting the regulator
from its input voltage. This results in a ÒcrowbarÓ action to
clamp the output voltage and prevents damage to the load.
The regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low.
It is important that in both circuits, the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) and GATE
pins.
Additionally, a dedicated Overvoltage protection (OVP)
output pin (pin 21) is provided in the CS5132. The OVP sig-
nal will go high (overvoltage condition), if the output volt-
age (VCC(CORE)) exceeds the regulation voltage by 8.5% of
the voltage set by the particular DAC code. The OVP pin
can source up to 25mA of current that can be used to drive
an SCR to crowbar the power supply.
15
To V
I/O
GATE
Power Switch
CS5132
R
1
13
COMP2
Power-Good Circuit
C
2
COMP2
The Power-Good pin (pin 22) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled up, and is pulled low (below 0.3V) when the regula-
tor output voltage typically exceeds ± 8.5% of the nominal
output voltage. Maximum output voltage deviation before
Power-Good is pulled low is ± 12%.
C
1
R
Figure 7: Slope compensation for the non-synchronous regulator section
(VI/O).
Output Enable
On/off control of the regulator outputs can be implement-
ed by pulling the COMP pins low. It is required to pull the
COMP pins below the 1.06V PWM comparator offset volt-
age in order to disable switching on the GATE drivers.
10
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
