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CS5124XD8 参数 Datasheet PDF下载

CS5124XD8图片预览
型号: CS5124XD8
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能,集成的电流模式PWM控制器 [High Performance, Integrated Current Mode PWM Controllers]
分类和应用: 控制器
文件页数/大小: 10 页 / 174 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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CS5124/6
Application Information: continued
The Line BIAS pin shows a significant change in the regu-
lated V
CC
voltage when sinking large currents. This will
show up as poor line regulation with a low value pull-up
resistor. Typical regulated V
CC
vs BIAS pin sink current is
shown in Figure 1.
8.3
the rising edge of the Gate is shown in Figure 4. When this
pin is held high or low the internal clock determines the
oscillator frequency.
SYNC
OSC
GATE
8.2
V
CC
8.1
Figure 3. Synchronized Operation
8
140
7.9
10µA
20µA
50µA
100µA
200µA
130
Phase Lag°
Bias Current (I
BIAS
)
Figure 1. Regulated V
CC
vs BIAS Sink Current
120
110
100
90
80
70
200kHz
300kHz
400kHz
500kHz
600kHz
Clock Synchronization Pin (CS5126 Only)
The CS5126 can be synchronized to signals ranging from
30% slower to several times faster than the internal oscilla-
tor frequency. If the part is synchronized to a fast signal,
maximum duty cycle will be reduced as the frequency
increases as shown in Figure 2.
Figure 4 : Typical Phase Lag between SYNC and GATE on.
0.82
Gate Drive
Maximum Duty Cycle
125°C
25°C
-40°C
0.77
Rail to rail gate driver operation can be obtained (up to
13.5V) over a range of MOSFET input capacitance if the
gate resistor value is kept low. Figure 5 shows the high
gate drive level vs. the series gate resistance with V
CC
= 8V
driving an IRF220.
0.72
200kHz
300kHz
400kHz
Frequency
500kHz
600kHz
8.5
8
Peak Voltage
Figure 2: CS5126 Maximum Duty Cycle vs Frequency (Synchronized
Operation)
7.5
7
6.5
6
0
0.3
0.5
2.5
5
11
Gate Resistor Value
If the converter is initially free running and a sync signal is
applied, the current oscillator cycle will terminate and the
oscillator will lock on to the sync signal. The SYNC pin
works with a positive edge triggered signal. When the sync
signal transitions high the current PWM cycle terminates
and a new cycle begins as shown in Figure 3. The typical
phase lag between the rising edge of the SYNC signal and
Figure 5. Gate Drive vs Gate Resistor Driving an IRF220 (V
CC
= 8V)
7