CS5124/6
Block Diagram
{CS5126 ONLY}
SYNC
V
CC
UVLO COMP
V
CC
OSC
DIS
G2
ENABLE
F3
R
F1
DRIVER
Q
V
CC
+
+
-
V
7.7 V/7.275V
V
REF
= 5V
Q
G1
S
R
GATE
RAMP
S
V5
REF
RESET DOMAIN
{85 mV/us}
170mV us
G7
G3
V5
REF
4500Ω
V
REFOK
LINE UVLO COMP
V
+
V5
REF
10µA
TSHUT
150°C/125°C
+
V
2.62 V/2.45V
V
FB
COMP
UVLO
+
-
BIAS
(CS5124 ONLY)
V
1.91 V/1.83V
+
SOFT START LATCH
F2
V
CC
2.9 R
G5
-
2ND I
COMP
+
V
{525mV}
275mV
BLANKING
BLANK
G6
S
R
Q
{2.65V}
2.90V
+
V
2.0V
V
+
R
SS COMP
275mV
V
SS
Powering the IC
V
CC
can be powered directly from a regulated supply
and requires 500µA of start-up current. The CS5124/6
includes a line bias pin (BIAS) that can be used to control a
series pass transistor for operation over a wide input volt-
age. The BIAS pin will control the gate voltage of an N-
channel MOSFET placed between V
IN
and V
CC
to regulate
V
CC
at 8V.
V
CC
and UVLO Pins
The UVLO pin has three different modes; low power shut-
down, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that V
IN
, as shown in
the application schematic, is ramped up starting at 0V with
the UVLO pin open. The SS and I
SENSE
pins also start at 0V.
While the UVLO is below 1.8V, the IC will remain in a low
current sleep mode and the BIAS pin of the CS5124 is inter-
nally clamped to a maximum of 15V. When the voltage on
the UVLO pin rises to between 1.8V and 2.6V the reference
for the V
CC
UVLO is enabled and V
CC
is regulated to 8V by
the BIAS pin (CS5124 only), but the IC remains in a UVLO
state and the output driver does not switch. When the
UVLO pin exceeds 2.6V and the V
CC
pin exceeds 7.7V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the I
SENSE
and V
FB
pins. The Soft Start capacitor begins charging from 0V at
5
+
-
+
-
LINE AMP
SET DOMAIN
V5
REF
+
-
SS AMP
+
1.32V
+
V
Theory of Operation
10µA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the V
FB
pin and the V
FB
volt-
age begins to rise. As V
FB
rises the duty cycle increases
until the supply comes into regulation.
Soft Start
Soft Start is accomplished by clamping the V
FB
pin 1.32V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124/6 starts, the Soft
Start capacitor is charged from a 10µA source from 0V to
4.9V. The V
FB
pin follows the Soft Start pin offset by –1.32V
until the supply comes into regulation or until the Soft
Start error amp is clamped at 2.9V (2.65V for the CS5126).
During fault conditions the Soft Start capacitor is dis-
charged at 10mA.
Fault Conditions
The CS5124/6 recognizes the following faults: UVLO off,
Thermal Shutdown, V
REF(OK)
, and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft Start capacitor. Soft Start will begin
only after all faults have been removed and the Soft Start
capacitor has been discharged to less than 0.275V. Each
fault will be explained in the following sections.
+
-
REMOTE
(SLEEP) COMP
+
PWM COMP
+
{125mV}
60mV
+
-
+
-
+
-
+
V
490mV
{1/5}
1/10
÷
V
V
FB
1000Ω
I
SENSE
Gnd
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
