Application Information: continued
Typical Performance Characteristics
Design Guidelines
Switch Frequency and Maximum Duty Cycle Calculations
Oscillator timing capacitor, C
T
, is charged by V
REF
through
R
T
and discharged by an internal current source. During
the discharge time, the internal clock signal sets the Gate
output to the low state, thus providing a user selectable
maximum duty cycle clamp. Charge and discharge times
are determined by following general formulas;
CS51221
t
C
= R
T
C
T
ln
(
(V
REF
- V
VALLEY
)
(V
REF
- V
PEAK
)
)
)
,
Figure 6: The Sync pin generates a sync pulse at the beginning of each
switching cycle. CH2: GATE Pin, CH3: R
T
C
T,
CH4: SYNC pin.
t
d
= R
T
C
T
ln
(
(V
REF
- V
PEAK
- I
d
R
T
)
(V
REF
- V
VALLEY
- I
d
R
T
)
The bi-directional SYNC pin can also receive an external
sync signal of a greater frequency. As show in Fig.7, when
the SYNC pin is triggered by an incoming signal, the IC
immediately discharges C
T
. The GATE signal is turned on
once the R
T
C
T
pin reaches the valley voltage. Because of
the steep falling edge, this valley voltage falls below the
regular 1V threshold. However, the R
T
C
T
pin voltage is
then quickly raised by a clamp. When the R
T
C
T
pin reaches
the 0.95V(typ) Valley Clamp Voltage, the clamp is discon-
nected after a brief delay and C
T
is charged through R
T
.
where
t
C
= charging time;
t
d
= discharging time;
V
VALLEY
= valley voltage of the oscillator;
V
PEAK
= peak voltage of the oscillator.
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 3.3V, V
VALLEY
= 1V, V
PEAK
= 2V, I
d
= 1mA
t
C
= 0.57R
T
C
T
t
d
= R
T
C
T
ln
(
1.3 - 0.001R
T
2.3- 0.001R
T
0.57
)
)
D
max
=
0.57+ In
(
1.3 - 0.001R
T
2.3- 0.001R
T
It is noticed from the equation that for the oscillator to
function properly, R
T
has to be greater than 2.3k.
Figure 7: Operation with external sync. CH 2: SYNC pin, CH3: Gate pin,
G4: R
T
C
T
pin.
9
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
