CS5111
Circuit Description
V
REG
Over Voltage
+
-
1.25V
Current
Limit
Over
Temperature
I
BIAS
R
BIAS
64.9kΩ
C
delay
WDI
Bandgap
Reference
RESET &
Watchdog Timer
Figure 2. Block diagram of 5V linear regulator portion of the CS5111.
R
1
Linear
Error
Amplifier
Q
2
Q
1
Q
3
R
2
R
3
R
4
R
5
RESET
V
LIN
C
OUT
= 100µF
ESR < 8Ω
5V Linear Regulator
The 5V linear regulator consists of an error amplifier,
bandgap voltage reference, and a composite pass transistor.
The 5V linear regulator circuitry is shown in Figure 2.
When an unregulated voltage greater than 6.6V is applied
to the V
REG
input, a 5V regulated DC voltage will be pre-
sent at V
LIN
. For proper operation of the 5V linear regula-
tor, the I
BIAS
lead must have a 64.9kΩ pull down resistor to
ground. A 100µF or larger capacitor with an ESR <8Ω
must be connected between V
LIN
and ground. To operate
the 5V linear regulator as an independent regulator (i.e.
separate from the switching supply), the input voltage
must be tied to the V
REG
lead.
As the voltage at the V
REG
input is increased, Q
1
is turned
on. Q
1
provides base drive for Q
2
which in turn provides
base current for Q
3
. As Q
3
is turned on, the output voltage,
V
LIN
, begins to rise as Q
3
’s output current charges the out-
put capacitor, C
OUT
. Once V
LIN
rises to a certain level, the
error amplifier becomes biased and provides the appropri-
ate amount of base current to Q
1
. The error amplifier mon-
itors the scaled output voltage via an internal voltage
divider, R
2
through R
5
, and compares it to the bandgap
voltage reference. The error amplifier output or error sig-
nal is an output current equal to the error amplifier’s input
differential voltage times the transconductance of the
amplifier. Therefore, the error amplifier varies the base
current to Q
1
, which provides bias to Q
2
and Q
3
, based on
the difference between the reference voltage and the
scaled V
LIN
output voltage.
Control Functions
Using C
Delay
= 0.1µF and R
BIAS
= 64.9kΩ gives a time rang-
ing from 6.25ms to 11ms assuming ideal components. Based
on this, the software must be written so that the watchdog
arrives at least every 6.25ms. In practice, the tolerance of
C
Delay
and R
BIAS
must be taken into account when calculat-
ing the minimum watchdog time (t
WDI
).
V
REG
RESET
WDI
V
LIN
t
POR
Normal Operation
Figure 3. Timing diagram for normal regulator operation.
V
REG
50% Duty
Cycle
RESET
WDI
The watchdog timer circuitry monitors an input signal
(WDI) from the microprocessor. It responds to the falling
edge of this watchdog signal which it expects to see within
an externally programmable time (see Figure 3).
The watchdog time is given by:
t
WDI
= 1.353
×
C
Delay
R
BIAS
5
V
LIN
t
POR
A
A: Watchdog waiting for
low-going transition on
WDI
B
B: RESET stays low for
t
WDI
time.
Figure 4. Timing diagram when WDI fails to appear within the preset
time interval, t
WDI
.
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
