CS51031
Block Diagram
V
REF
I
C
C
OSC
7I
C
RG
Oscillator
Comparator
A1
G1
V
GATE
Flip-Flop
R
F2
G2
1.5V
V
CC
V
CC
V
CC
OK
V
REF
3.3V
-
V
REF
= 3.3V
G3
I
T
CS
CS
Comparator
A2
I
T
5
1.5V
2.5V
Fault
Comp
V
C
V
GATE
Q
PGnd
Q
-
A6
+
Hold
Off
Comp
S
V
FB
Comparator
V
FB
1.25V
2.5V
+
-
0.7V
G4
+ 1.15V
CS Charge
Sense
Comparator
A4
+
-
2.3V
R
F1
G5
S
Q
I
T
55
Q
Slow Discharge
Flip-Flop
A3
+
Slow Discharge
Comparator
Gnd
2.4V
Figure 1: Block Diagram for CS51031
Circuit Description
Theory of Operation
Control Scheme
The CS51031 monitors and the output voltage to determine
when to turn on the PFET. If V
FB
falls below the internal
reference voltage of 1.25V during the oscillatorÕs charge
cycle, the PFET is turned on and remains on for the dura-
tion of the charge time. The PFET gets turned off and
remains off during the oscillatorÕs discharge time with the
maximum duty cycle to 80%. It requires 7mV typical, and
20mV maximum ripple on the V
FB
pin is required to oper-
ate. This method of control does not require any loop sta-
bility compensation.
Startup
The CS51031 has an externally programmable soft start fea-
ture that allows the output voltage to come up slowly, pre-
venting voltage overshoot on the output.
At startup, the voltage on all pins is zero. As V
CC
rises, the
V
C
voltage along with the internal resistor R
G
keeps the
PFET off. As V
CC
and V
C
continue to rise, the oscillator
capacitor (C
OSC
) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. C
OSC
gets
charged by the current source I
C
and CS gets charged by
the I
T
source combination described by:
I
CS
= I
T
-
(
I
T
I
T
+
.
55
5
)
The internal Holdoff Comparator ensures that the external
PFET is off until V
CS
> 0.7V, preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the V
FB
comparatorÕs (A6)
reference input to approximately 1/2 of the voltage at the
CS pin during startup, permitting the control loop and the
output voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
feedback to the V
FB
Comparator sets the GATE flip-flop
during C
OSC
Õs charge cycle. Once the GATE flip-flop is set,
V
GATE
goes low and turns on the PFET. When V
CS
exceeds
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
