CS51021/22/23/24
Circuit Description: continued
The maximum duty cycle is set by the ratio of the on time,
t
ON
, and the whole period,
T = t
ON
+ t
OFF
. Because the
timing capacitor’s discharge current is trimmed, the maxi-
mum duty cycle is well defined. It is determined by the
ratio between the timing resistor R
T
and the timing capaci-
tor C
T
. Refer to figures 5 and 6 to select appropriate values
for R
T
and C
T.
1
f
SW
= T
; T
SW
= t
CH
+ t
DIS
SW
2500
50
1
2000
1. C
T
= 47pF
2. C
T
= 100pF
3. C
T
= 150pF
4. C
T
= 220pF
5. C
T
= 390pF
6. C
T
= 470pF
7. C
T
= 560pF
8. C
T
= 680pF
40
5
10
15
20
25
30
35
40
45
50
55
100
7
6
90
5
8
80
4
3
2
1. C
T
= 47pF
2. C
T
= 100pF
3. C
T
= 150pF
4. C
T
= 220pF
5. C
T
= 390pF
6. C
T
= 470pF
7. C
T
= 560pF
8. C
T
= 680pF
Duty Cycle (%)
70
1
60
R
T
(kΩ)
Frequency (kHz)
1500
Figure 6: Duty Cycle vs. R
T
for Discrete Capacitor Values.
2
1000
3
4
500
5
6
8
0
5
10
7
15
20
25
30
35
40
45
50
R
T
(kΩ)
Figure 5: Frequency vs. R
T
for Discrete Capacitor Values.
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
