CS4172
Electrical Characteristics: -40¡C ² T
A
² 105¡C; 7.5V ² V
BB
² 14V; 4.5V ² V
CC
² 5.5V (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shift Clock Frequency
SCLK High Time
SCLK Low Time
SO Rise Time
SO Fall Time
SO Delay Time
SI Setup Time
SI Hold Time
CS Setup Time
CS Hold Time
0.75V to V
CC
- 1.2V; C
L
= 90pF
0.75V to V
CC
- 1.2V; C
L
= 90pF
C
L
= 90pF
2.0
175
175
150
150
150
75
75
0
75
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Package Pin Description
PACKAGE PIN#
PIN SYMBOL
FUNCTION
16 Lead SO Wide
1
2
3
4,5,12,13
6
7
16 Lead PDIP
1
2
4
3,13,14
6
7
SIN
-
SIN
+
V
BB
Gnd
SI
V
CC
Negative output for SINE coil.
Positive output for SINE coil.
Analog supply. Nominally 13.5V.
Ground.
Serial data input. Data present at the rising edge of the
clock signal is shifted into the internal shift register.
5V logic supply. The internal registers and latches are
reset by a POR generated by the rising edge of the voltage
on this pin.
Controls the state of the output buffers. A logic low on
this pin turns them off.
Serial clock for shifting in/out of data. Rising edge shifts
data on SI into the shift register and the falling edge
changes the data on SO.
When high allows data at SI to be shifted into part with
the rising edges of SCLK. The falling edge transfers the
shift register contents into the DAC and multiplexer to
update the output buffers. The falling edge also re-enables
the output drivers if they have been disabled by a fault.
STATUS reflects the state of the outputs and is low any-
time the outputs are disabled, either by OE or the internal
protection circuitry. Requires external pull-up resistor.
Serial data output. Existing 10-bit data is shifted out when
new data is shifted in. Allows cascading of multiple
devices on common serial port.
Negative output for COSINE coil.
Positive output for COSINE coil.
No connection.
8
9
8
9
OE
SCLK
10
10
CS
11
11
ST
14
5
SO
15
16
15
16
12
COS
-
COS
+
NC
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
